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Toolchain Anomalies

The anomalies will only be worked around if the anomaly exists on the specific version of silicon that was targetted during the -mcpu=.



The following instructions can sometimes operate incorrectly when the preceding instruction is creating the operand for the instruction. The affected instructions are:


An example is shown for the Signbits instruction:

  r0 = ashift r2 by r3.l;
  r1.l = signbits r0;


  1. Precede signbits instructions with a nop:
    r0 = ashift r2 by r3.l;
          r1.l = signbits r0;


  2. Make sure the operand register for the signbits is not dependent on the previous instruction:
          r0 = ashift r2 by r3.l;
          // ** another useful instruction that is not updating r0 **;
          r1.l = signbits r0;

The Blackfin run-time libraries avoid the anomaly conditions when necessary.

If necessary the gcc compiler should insert a NOP instruction between two instructions where the first instruction assigns a value to a DREG, and the second instruction uses the DREG as a parameter to a SIGNBITS, EXTRACT, DEPOSIT or EXPADJ instruction.