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System Synchronize

General Form



SSYNC ; /* (a) */

Instruction Length

In the syntax, comment (a) identifies 16-bit instruction length.

Functional Description

The System Synchronize (SSYNC) instruction forces all speculative, transient states in the core and system to complete before processing continues. Until SSYNC completes, no further instructions can be issued to the pipeline.

The SSYNC instruction performs the same function as Core Synchronize (CSYNC). In addition, SSYNC flushes any write buffers (between the L1 memory and the system interface) and generates a Synch request signal to the external system. The operation requires an acknowledgement Synch_Ack signal by the system before completing the instruction.

If the idle_req bit of the SEQSTAT register is set when SSYNC is executed, the processor enters Idle state and asserts the external Idle signal after receiving the external Synch_Ack signal. After the external Idle signal is asserted, exiting the Idle state requires an external Wakeup signal.

SSYNC should be issued immediately before and after writing to a system MMR. Otherwise, the MMR change can take effect at an indeterminate time while other instructions are executing, resulting in imprecise behavior.

Flags Affected


Required Mode

User & Supervisor

Parallel Issue

The SSYNC instruction cannot be issued in parallel with other instructions.


Consider the following example code sequence.

if cc jump away_from_here ; /* produces speculative branch
prediction */
ssync ;
r0 = [p0] ; /* load */

In this example, SSYNC ensures that the load instruction will not be executed speculatively. The instruction ensures that the conditional branch is resolved and any entries in the processor store buffer and write buffer have been flushed. In addition, all exceptions complete processing before SSYNC completes.

Also See

Special Applications

Typically, SSYNC prepares the architecture for clock cessation or frequency change. In such cases, the following instruction sequence is typical.

    CLI r0 ;       /* disable interrupts */
    idle ;         /* enable Idle state */
    ssync ;        /* conclude all speculative states, assert external
                    * Sync signal, await Synch_Ack, then assert external Idle signal
                    * and stall in the Idle state until the Wakeup signal. Clock input
                    * can be modified during the stall. */
    sti r0 ;       /* re-enable interrupts when Wakeup occurs */