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DTEST

When the Data Test Command register (DTEST_COMMAND) is written to, the L1 cache data or tag arrays are accessed, and the data is transferred through the Data Test Data registers (DTEST DATA[1:0]).

Access to these registers is possible only in Supervisor or Emulation mode.

When writing to DTEST registers, always write to the DTEST_DATA registers first, then the DTEST_COMMAND register.

To use the DTEST mechanism to perform a write, put write data into DTEST_DATA[1:0] registers, then write to DTEST_COMMAND register, then perform CSYNC. As CSYNC is completed, the operation will be performed.

To use the DTEST mechanism to perform a read, write the DTEST_COMMAND register then perform a CSYNC. After the CSYNC completes, the read data will be available in the DTEST_DATA[1:0] registers.

The DTEST set of registers is used to access Databank A and Databank B whether configured as cache or SRAM. It also is used to access Instruction banks A and B, which are SRAM-only banks.

DTEST_COMMAND Register

When the Data Test Command register (DTEST_COMMAND) is written to, the L1 cache data or tag arrays are accessed, and the data is transferred through the Data Test Data registers (DTEST DATA[1:0]). The Data/Instruction Access bit allows direct access via the DTEST_COMMAND MMR to L1 instruction SRAM.

Register

Software example

Turn address into DTEST_COMMAND

file: arch/blackfin/mm/isram-driver.c

scm failed with exit code 1:
file does not exist in git

Read ISRAM

file: arch/blackfin/mm/isram-driver.c

scm failed with exit code 1:
file does not exist in git

Write ISRAM

file: arch/blackfin/mm/isram-driver.c

scm failed with exit code 1:
file does not exist in git