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DEPOSIT

General Form

dest_reg = DEPOSIT ( backgnd_reg, foregnd_reg )
dest_reg = DEPOSIT ( backgnd_reg, foregnd_reg ) (X)

Syntax

Dreg = DEPOSIT ( Dreg, Dreg ) ; /* no extension (b) */
Dreg = DEPOSIT ( Dreg, Dreg ) (X) ; /* sign-extended (b) */

Syntax Terminology

Dreg
R7–0

Instruction Length

In the syntax, comment (b) identifies 32-bit instruction length.

Functional Description

The Bit Field Deposit instruction merges the background bit field in backgnd_reg with the foreground bit field in the upper half of foregnd_reg and saves the result into dest_reg. The user determines the length of the foreground bit field and its position in the background field. The input register bit field definitions appear in Table 13-1.

Table 13-1. Input Register Bit Field Definitions

reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
backgnd_reg b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b
foregnd_reg n n n n n n n n n n n n n n n n x x x p p p p p x x x L L L L L

where:

  • b = background bit field (32 bits)
  • n = foreground bit field (16 bits); the L field determines the actual number of foreground bits used.
  • p = intended position of foreground bit field LSB in dest_reg: valid range 0 through 31
  • L = length of foreground bit field:valid range 0 through 16

The operation writes the foreground bit field of length L over the background bit field with the foreground LSB located at bit p of the background. See “Example,” below, for more.

Boundary Cases

Consider the following boundary cases.

  • Unsigned syntax, L = 0: The architecture copies backgnd_reg contents without modification into dest_reg. By definition, a foreground of zero length is transparent.
  • Sign-extended, L = 0 and p = 0: This case loads 0x0000 0000 into dest_reg. The sign of a zero length, zero position foreground is zero; therefore, sign-extended is all zeros.
  • Sign-extended, L = 0 and p = 0: The architecture copies the lower order bits of backgnd_reg below position p into dest_reg, then sign-extends that number. The foreground value has no effect.
    For instance, if: backgnd_reg = 0x0000 8123, L = 0, and p = 16, then:
    dest_reg = 0xFFFF 8123.
    In this example, the architecture copies bits 15–0 from backgnd_reg into dest_reg, then sign-extends that number.
  • Sign-extended, (L + p) > 32: Any foreground bits that fall outside the range 31–0 are truncated.

The Bit Field Deposit instruction does not modify the contents of the two source registers. One of the source registers can also serve as dest_reg.

Options

The (X) syntax sign-extends the deposited bit field. If you specify the sign-extended syntax, the operation does not affect the dest_reg bits that are less significant than the deposited bit field.

Flags Affected

This instruction affects flags as follows.

  • AZ is set if result is zero; cleared if nonzero.
  • AN is set if result is negative; cleared if non-negative.
  • AC0 is cleared.
  • V is cleared.
  • All other flags are unaffected.

The ADSP-BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products. For more information on the ADSP-BF535 status flags, see Table A-1 on page A-3.

Required Mode

User & Supervisor

Parallel Issue

This instruction can be issued in parallel with specific other 16-bit instructions. For details, see “Issuing Parallel Instructions” on page 20-1.

Examples

Bit Field Deposit Unsigned

r7 = deposit (r4, r3) ;

Example 1

  • R4=0b1111 1111 1111 1111 1111 1111 1111 1111 where this is the background bit field
  • R3=0b0000 0000 0000 0000 0000 0111 0000 0011 where bits 31–16 are the foreground bit field, bits 15–8 are the position, and bits 7–0 are the length

then the Bit Field Deposit (unsigned) instruction produces:

  • R7=0b1111 1111 1111 1111 1111 1100 0111 1111

Example 2

  • R4=0b1111 1111 1111 1111 1111 1111 1111 1111 where this is the background bit field
  • R3=0b0000 0000 1111 1010 0000 1101 0000 1001 where bits 31–16 are the foreground bit field, bits 15–8 are the position, and bits 7–0 are the length

then the Bit Field Deposit (unsigned) instruction produces:

  • R7=0b1111 1111 1101 1111 0101 1111 1111 1111

Bit Field Deposit Sign-Extended

r7 = deposit (r4, r3) (x) ; /* sign-extended*/

Example 1

  • R4=0b1111 1111 1111 1111 1111 1111 1111 1111 where this is the background bit field
  • R3=0b0101 1010 0101 1010 0000 0111 0000 0011 where bits 31–16 are the foreground bit field, bits 15–8 are the position, and bits 7–0 are the length

then the Bit Field Deposit (unsigned) instruction produces:

  • R7=0b0000 0000 0000 0000 0000 0001 0111 1111

Example 2

  • R4=0b1111 1111 1111 1111 1111 1111 1111 1111 where this is the background bit field
  • R3=0b0000 1001 1010 1100 0000 1101 0000 1001 where bits 31–16 are the foreground bit field, bits 15–8 are the position, and bits 7–0 are the length

then the Bit Field Deposit (unsigned) instruction produces:

  • R7=0b1111 1111 1111 0101 1001 1111 1111 1111

Also See

Special Applications

Video image overlay algorithms