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CACHE CONTROL

This chapter discusses the instructions that are used to flush, invalidate, and prefetch data cache lines as well as the instruction used to invalidate a line in the instruction cache.

As part of the data-cache related instructions, the PREFETCH instruction can be used to improve performance by initiating a data cache-line fill in advance of when the desired data is actually required for processing. The FLUSH instruction is useful when data cache is configured in the write-back mode (which is described in further detail in the “Memory” chapter). This instruction forces data in the cache line that has been changed by the processor (and thus has been marked as “dirty”) to be written to its source memory.

There is no single instruction that can be used to invalidate a data cache-line. The FLUSHINV instruction provides a way to directly flush and invalidate a data cache-line. The FLUSHINV instruction is commonly used to invalidate a buffer, but the instruction also performs a flush of data marked as “dirty.” The ITEST and DTEST registers, which are described in their own sections, can also be used to directly invalidate a line in cache. Buffers in source memory need to be invalidated when a DMA channel is filling the buffer and data cache has been enabled and the source memory has been defined as cacheable. By invalidating the cache-lines associated with the buffer, “coherency” is maintained between the contents stored in cache and the actual values in source memory. When the buffer size is less than or equal in size to the actual cache on the processor, it is better to use the FLUSHINV instruction in a loop to invalidate the cache-lines. When the buffer is larger in size than the cache, it is better to use the DTEST registers described in the “Memory” chapter to invalidate the cache-lines.

The IFLUSH instruction is used to invalidate an instruction cache-line. On the Blackfin processors, the cache-line size is 32 bytes.

Instruction Summary