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BITMUX

General Form

BITMUX ( source_1, source_0, A0 ) (ASR)
BITMUX ( source_1, source_0, A0 ) (ASL)

Syntax

BITMUX ( Dreg , Dreg , A0 ) (ASR) ; /* shift right, LSB is shifted out (b) */
BITMUX ( Dreg , Dreg , A0 ) (ASL) ; /* shift left, MSB is shifted out (b) */

Syntax Terminology

Dreg
R7–0

Instruction Length

In the syntax, comment (b) identifies 32-bit instruction length.

Functional Description

The Bit Multiplex instruction merges bit streams.

The instruction has two versions, Shift Right and Shift Left. This instruction overwrites the contents of source_1 and source_0. See table below:

source_1 and source_0 must not be the same D-register

Contents Before Shift

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
source_1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
source_0 y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y
Accumulator A0 z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z

In the Shift Right version, the processor performs the following sequence:

  1. Right shift Accumulator A0 by one bit. Right shift the LSB of source_1 into the MSB of the Accumulator.
  2. Right shift Accumulator A0 by one bit. Right shift the LSB of source_0 into the MSB of the Accumulator.

Shift Right Instruction

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
source_1 1) 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
source_0 2) 0 y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y
Accumulator A0 3) y x z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z

In the Shift Left version, the processor performs the following sequence:

  1. Left shift Accumulator A0 by one bit. Left shift the MSB of source_0 into the LSB of the Accumulator.
  2. Left shift Accumulator A0 by one bit. Left shift the MSB of source_1 into the LSB of the Accumulator.

Shift Left Instruction

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
source_1 4) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
source_0 5) x y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y 0
Accumulator A0 6) z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z y x

Flags Affected

None

The ADSP-BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products. For more information on the ADSP-BF535 status flags, see Table A-1 on page A-3.

Required Mode

User & Supervisor

Parallel Issue

This instruction can be issued in parallel with specific other 16-bit instructions. For details, see “Issuing Parallel Instructions”.

Example

bitmux (r2, r3, a0) (asr) ;   /* right shift*/

Example 1

If the input is:

  • R2=0b1010 0101 1010 0101 1100 0011 1010 1010
  • R3=0b1100 0011 1010 1010 1010 0101 1010 0101
  • A0=0b0000 0000 0000 0000 0000 0000 0000 0000 0000 0111

then the Shift Right instruction produces:

  • R2=0b0101 0010 1101 0010 1110 0001 1101 0101
  • R3=0b0110 0001 1101 0101 0101 0010 1101 0010
  • A0=0b1000 0000 0000 0000 0000 0000 0000 0000 0000 0001
bitmux (r3, r2, a0) (asl) ; /* left shift*/

Example 2

If the input is:

  • R3=0b1010 0101 1010 0101 1100 0011 1010 1010
  • R2=0b1100 0011 1010 1010 1010 0101 1010 0101
  • A0=0b0000 0000 0000 0000 0000 0000 0000 0000 0000 0111

then the Shift Left instruction produces:

  • R2=0b1000 0111 0101 0101 0100 1011 0100 1010
  • R3=0b0100 1011 0100 1011 1000 0111 0101 0100
  • A0=0b0000 0000 0000 0000 0000 0000 0000 0000 0001 1111

Also See

None

Special Applications

Convolutional encoder algorithms

1) , 2) is shifted right 1 place
3) is shifted right 2 place
4) , 5) is shifted left 1 place
6) is shifted left 2 places