world leader in high performance signal processing
Trace: » bitclr

BITCLR

General Form

 BITCLR ( register, bit_position )

Syntax

BITCLR ( Dreg , uimm5 ) ; /* (a) */

Syntax Terminology

Dreg
R7–0
uimm5
5-bit unsigned field, with a range of 0 through 31

Instruction Length

In the syntax, comment (a) identifies 16-bit instruction length.

Functional Description

The Bit Clear instruction clears the bit designated by bit_position in the specified D-register. It does not affect other bits in that register. The bit_position range of values is 0 through 31, where 0 indicates the LSB, and 31 indicates the MSB of the 32-bit D-register.

Flags Affected

The Bit Clear instruction affects flags as follows.

  • AZ is set if result is zero; cleared if nonzero.
  • AN is set if result is negative; cleared if non-negative.
  • AC0 is cleared.
  • V is cleared.
  • All other flags are unaffected.

The ADSP-BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products. For more information on the ADSP-BF535 status flags, see Table A-1 on page A-3.

Required Mode

User & Supervisor

Parallel Issue

This instruction cannot be issued in parallel with other instructions.

Example

bitclr (r2, 3) ; /* clear bit 3 (the fourth bit from LSB) in R2 */

For example, if R2 contains 0xFFFFFFFF before this instruction, it contains 0xFFFFFFF7 after the instruction.

Also See

Special Applications

None