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BF548 EZ-Kit Getting Started


This provides specific information to assist you with development of programs for the ADSP-BF548 EZ-KIT Lite evaluation system.

The ADSP-BF548 EZ-KIT Lite® provides developers with a cost-effective method for initial evaluation of the ADSP-BF54x Blackfin® Processors via a industry standard GNU Toolchain based development environment. With this EZ-KIT Lite, users can learn more about the Analog Devices (ADI) ADSP-BF548 hardware and software development, and quickly prototype a wide range of applications.

The EZ-KIT Lite includes an ADSP-BF548 Blackfin Processor desktop evaluation board along with complete development suite of the GNU Toolchain development and debugging environment, including the C/C++/Fortran compiler, assembler, and linker.

The EZ-KIT Lite ships with:

BF54x Block diagram

ADSP-BF542/BF544/BF547/BF548/BF549 Block diagram:


BF548 Demo

Here is a short video of some of some examples which can be run on the BF548 EZKit.

The Adobe Flash Plugin is needed to display this content.

Since we will not be distributing binaries externally for the media processing elements which can be found this the above video, you are on your own to recreate them. It should just be a simple matter of compiling the uclinux-dist.

Package Contents

Your ADSP-BF548 EZ-KIT Lite evaluation system package contains the following items.

  • ADSP-BF548 EZ-KIT Lite board
  • Universal 7.5V DC power supply
  • 256 MB secure digital (SD) memory card
  • 1 GB USB high-speed flash drive
  • 7-foot Ethernet crossover cable
  • 7-foot Ethernet patch cable
  • Four x 6-foot 3.5 mm male-to-male audio cables
  • 3.5 mm headphones
  • 5-in-1cable and connectors for USB on-the-go (OTG) applications
  • Ethernet loopback connector

It also may include things not needed for Linux development including:

  • 10-foot USB A-B male cable for USB Debug Agent
  • VisualDSP++ Installation Quick Reference Card
  • CD containing, VisualDSP++ software, ADSP-BF548 EZ-KIT Lite debug software, and the ADSP-BF548 EZ-KIT Lite Evaluation System Manual in pdf.

Default Configuration

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.

When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which can damage some components. Figure below shows the default jumper settings, switches, connector locations, and LEDs used in installation. Confirm that your board is in the default configuration before using the board.

U-Boot Installation and Session Startup

The default EZ-Kit setup has test LDRs in the parallel NOR flash and the SPI flash. You have two choices to get U-Boot setup initially:

  • Boot over the UART and write U-Boot to one of the flashes
    1. build U-Boot with BFIN_BOOT_MODE set to BFIN_BOOT_UART in include/configs/bf548-ezkit.h
    2. set the Boot Mode to UART boot (SW1 to 7)
    3. Load it over the UART.
    4. build U-Boot with BFIN_BOOT_MODE set to BFIN_BOOT_SPI_MASTER in include/configs/bf548-ezkit.h
    5. Write the new U-Boot into flash
    6. set the Boot Mode to SPI Boot (SW1 to 3)
    7. reset the board

If you don't want to build the images from source, they can be found at the U-Boot Project. There should be files there for UART booting, Parallel Flash Booting, and SPI Flash booting.

  • Write U-Boot to one of the flashes using JTAG (gnICE, VDSP, IGLOO, JTAGBlue, or PEEDI)

Both methods are documented in loading.

It is possible to load U-Boot/Kernel into SPI and NAND flash, so that the orginal “Blinky”, can still be selected parallel flash.

Switch Settings

This section describes operation of the push buttons and switches. The push button and switch locations are shown below.

SW1 - Boot Mode

The rotary switch (SW1) determines the boot mode of the processor. The relevant BMODE settings are the same as the BF54x family. For the full list, see the BF54x datasheet.

SW1 Position Boot Mode
0 Idle - no booting
1 Boot LDR from parallel flash
3 Boot LDR from SPI flash
7 Boot LDR over the UART

SW2 - Keypad Enable Switch

The keypad enable switch (SW2) disconnects the keypad signals from the GPIO pins of the processor. When the switch is OFF, its associated GPIO signals can be used on the PPI1 port, host interface, or expansion interface.

EZ-KIT Lite Signal SW2 Switch Position (Default) Processor Signal
PPI1D15/HPD7/KPC3 1 (ON) PD15
PPI1D14/HPD6/KPC2 2 (ON) PD14
PPI1D13/HPD5/KPC1 3 (ON) PD13
PPI1D12/HPD4/KPC0 4 (ON) PD12
PPI1D11/HPD3/KPR3 5 (ON) PD11
PPI1D10/HPD2/KPR2 6 (ON) PD10

SW3 Rotary Encoder with Momentary Switch

The rotary encoder can be turned clockwise for an up count or counter-clockwise for a down count. The encoder also features a momentary switch that allows you to zero the counter. The rotary encoder can be disabled from the processor by using the rotary encoder enable switch (SW4).

SW4 - Rotary Encoder Enable Switch

The rotary encoder enable switch (SW4) disconnects the rotary encoder signals from the GPIO pins of the processor. When the switch is OFF, its associated GPIO signals can be used on the host interface.

EZ-KIT Lite Signal SW4 Switch Position (Default) Processor Signal
N/A 4 (OFF) N/A

SW5 - Push Button Enable Switch

The push button enable switch (SW5) disconnects the associated push button circuit from the GPIO pins of the processor. When SW5 is OFF, the associated GPIO signals can be used on the expansion interface, host interface, or STAMP (0.1” IDC) headers

Push Button EZ-KIT Lite Signal SW5 Switch Position (Default) Processor Signal

SW6 - CAN0 Enable Switch

The CAN0 enable switch (SW6) disconnects the CAN0 signals from the GPIO pins of the processor and deactivates the CAN0 transceiver (U21). When SW6 is in the default positions, the switch connects to CAN0; otherwise, the associated GPIO signal of SW6 can be used as a STAMP GPIO.

CAN0 Signal EZ-KIT Lite Signal SW6 Switch Position (Default) Processor Signal

SW7 - UART Enable Switch

The UART enable switch (SW7) disconnects the UART1 signals from the GPIO pins of the processor. When the switch is OFF, the associated GPIO signal of SW7 can be used elsewhere on the board.

EZ-KIT Lite Signal SW7 Switch Position (Default) Processor Signal
N/A 4 (OFF) N/A

SW8 - Audio Loopback Test Switch

The audio loopback test switch (SW8) connects the inputs signals of the audio interface to the output signals. This allows the EZ-KIT Lite to be placed in a loopback test mode for signal and circuit continuity and functionality. All positions of the switch should be ON when running POST. In all other cases, the switch should be kept OFF.

EZ-KIT Lite Input Signal SW8 Switch Position (Default) EZ-KIT Lite Output Signal

SW9 - Reset Push Button

The reset push button (SW9) resets all of the ICs on the board. One exception is the VDSP++ debug agent. This should only by an issue if you are debugging via JTAG and need to push the reset button. (It doesn't work well).

SW10–13 Programmable Flag Push Buttons

Four momentary push buttons (SW10–13) are provided for general-purpose user input. The buttons connect to the PB11–8 programmable flag pins of the processor. The push buttons are active high and, when pressed, send a high (1) to the processor. The push button enable switch (SW5) disconnects the push buttons from the corresponding PB signal.

Push Button EZ-KIT Lite Signal Processor Signal

SW14 - LCD/PPI Configuration Switch (SW14)

The LCD/PPI configuration switch (SW14) connects the GPIO pins of the processor to the LCD or PPI configuration pins:

  • position 1 connects PB4 to the data available output (DAV) of the touchscreen controller (U9).
  • position 2 connects PB5 to the pen interrupt output (PENIRQ) of the touchscreen controller (U9).
  • position 3 connects PB2 to the PPI1CLK multiplexter (U20). This allows you to connect the PPI1CLK to the clock signal generated on the expansion interface or the on-board 27 MHz oscillator (U19).
  • position 4 connects PE3 to the DISP signal of the LCD via the LCD data connector (P15).

When SW14 is OFF, its associated GPIO signals can be used on the expansion interface.

EZ-KIT Lite Signal SW14 Switch Position (Default) Processor Signal

Newer boards (Rev 1.4+) use PB4 instead of PJ11 for IRQ events: you may need to update arch/blackfin/mach-bf548/boards/ezkit.c in the kernel to suite your needs

SW15 - CAN1 Enable Switch

The CAN1 enable switch (SW15) disconnects the CAN1 signals from the GPIO pins of the processor and deactivates the CAN1 transceiver (U33). When SW15 is in the default positions, the switch connects to CAN1. When otherwise, the associated GPIO signal of SW15 can be used as a STAMP GPIO.

CAN1 Signal EZ-KIT Lite Signal SW15 Switch Position (Default) Processor Signal

SW16 - Peripheral Control Enable

The peripheral control enable (SW16) connects the GPIO pins of the processor to the enable pins of the audio codec, USB regulator, or Ethernet controller:

  • position 1 connects PB3 to the reset pin of the audio codec (U11). This allows the audio codec to be reset via software.
  • position 2 connects PE7 to the 5 volt VBUS USB regulator (VR1) and FET switch (U39). This allows the software to control the enable pins of both the regulator and the FET switch if the VBUS line is powered with 5 volts by some other host device. When in USB OTG host mode, the signal needs to be a logic 1. This will cause the EZ-KIT to supply the 5V to the VBUS line. When in USB OTG device mode, the signal needs to be a logic 0. This will allow the host device to power the VBUS line and allow the Blackfin processor to remain in device mode.
  • position 3 connects PE8 to the interrupt signal of the Ethernet controller (U14).
  • position 4 connects PB11 to the reset of burst flash memory. This allows the software to reset the burst flash. In order to use this signal as a reset for burst flash, SW5.4 needs to be set OFF. When the signal is used as a reset for the burst flash, the HOSTWAIT signal and PB4 are not be available. By default the switch is set to OFF and is not used.

When the switch is OFF, its associated GPIO signals can be used on the expansion interface.

EZ-KIT Lite Signal SW16 Switch Position (Default) Processor Signal

SW17 - LCD Module Configuration

The LCD module configuration switch (SW17) is used to set up the LCD module in 24-bit mode, 18-bit mode, or to disconnect the LCD in order to use the processor EPPI signals on other areas of the board. The default setting is for the LCD module to operate in 24-bit mode.

LCD Module Configuration in (SW17)

SW17 Switch Position (Default) Processor Signal EZ-KIT Lite Signal 24-bit Mode 18-bit Mode Disconnected
2 PPI0D[0–17] LCD_R[2–7]
3 PPI0D[0–17]

JP1 - UART1 Loopback

Make sure there is no jumper on JP1 otherwise the UART1 will be forced into loopback mode.

JP2 - SPI1 Enable

JP2 will enable SPI1 port while disconnecting LED1-6.

JP3 - Ethernet Speed

Make sure there is no jumper on JP3 otherwise the PHY will be forced to 10mbit and auto negotiation will be disabled.

Memory Map

The ADSP-BF548 EZ-KIT Lite board includes five types of external memory:

  • double data rate (DDR),
  • serial peripheral interconnect (SPI),
  • burst flash,
  • NAND, and
  • secure digital (SD).

DDR Interface

The ADSP-BF548 processor has a built-in double data rate (DDR) SDRAM controller, which connects to a Micron MT46V32M16 32M x 16 bits (64 MB) DDR memory chip. The controller connects to the DDR memory bank 0 via the ~DDRCS0 signal of the processor. The DDR memory chip is the only device connected to the processor’s DDR interface. The DDR interface can operate at a maximum system clock (SCLK) frequency of 133 MHz.

There is a trade-off between selecting the maximum core clock (CCLK) of the processor and the maximum system clock. Consequently, the respective control registers must be initialized appropriately to get either maximum CCLK or maximum SCLK.

Burst Flash Memory Interface

The burst flash memory interface of the ADSP-BF548 EZ-KIT Lite contains a 32 MB (16M x 16-bits) Intel PC28F128K3C115 chip. The flash memory connects gluelessly to the processor and is mapped to the processor’s external bank 0. This is accomplished by mapping the flash memory’s chip enable pin to the ~AMS0 memory select pin of the processor. The address range for the flash memory is 0x2000 0000 to 0x20FF FFFF. The flash is pre-loaded with boot code for the blink and power-on-self test (POST) programs. For more information, refer to “Power-On-Self Test” in the Board manual.

By default the EZ-KIT Lite boots from the 16-bit burst flash memory. The processor boots from the burst flash if the boot mode select switch (SW1) is set to a position of 1 (see “Boot Mode Select Switch (SW1)” below).

NAND Flash Interface

The ADSP-BF548 processor is equipped with an internal NAND flash controller, which allows the 2 Gbit ST Micro’s NAND02 device to be attached gluelessly to the processor. The NAND flash is attached via the processor’s specific NAND flash control lines and external eight-bit data bus on the EBIU interface. The NAND flash shares the data bus with the burst flash memory, Ethernet controller, ATAPI hard drive, and expansion interface. You can write to each of the mentioned peripherals, one peripheral at a time.

SPI Interface

The ADSP-BF548 processor has three serial peripheral interconnect (SPI) ports that share multi-function I/O pins. The processor’s SPI port 0 connects directly to serial flash memory, AD7877 touchscreen controller, and expansion interface.

The serial flash memory is a 16 Mb ST Micro M25P16 device, which is selected using the SPI0SEL1 flag pin of the processor. The SPI flash memory is pre-loaded with boot code for the blink and POST programs. For more information, refer to “Power-On-Self Test” in the Board manual. By default the EZ-KIT Lite boots from the 16-bit flash burst memory. The SPI flash can be used to boot up the processor by setting the boot mode select switch (SW1) to position 3 (see “Boot Mode Select Switch (SW1)” below).

SD Interface

The ADSP-BF548 processor has a secure digital (SD) interface. The interface consists of a CLK pin, a command pin, and a four-bit data bus. The SD interface of the processor gluelessly connects to the on-board memory. The SD interface pins are not shared with other peripherals on the board. The memory can be written to in both one-bit and four-bit modes. The EZ-KIT Lite is accompanied with a 256 MB SD memory card plugged into the SD memory card connector (J5).


EPPI Interface

The ADSP-BF548 processor provides up to three enhanced parallel peripheral interfaces (EPPIs), supporting data widths up to 24 bits. Each EPPI interface is a half-duplex, bi-directional bus consisting of up to 24 bits of data, a dedicated clock, and synchronization signals. The EZ-KIT Lite board utilizes two EPPI ports. One port connects to a TFT LCD module, while the other port connects to the expansion interface and the 0.1” PPI connector.

LCD Module Interface

The EZ-KIT Lite features a Sharp LQ043T1DG01 TFT LCD module. This is a 4.3” landscape display with a resolution of 480 x 272 (WQVGA) and a color depth of 18 or 24 bits.

Touchscreen Interface

The AD7877 touchscreen controller connects to the SPI0 interface. The controller provides the X and Y positions, as well as a measurement for the pressure applied to the touchscreen. The touchscreen can be used with either a stylus or a finger.

Keypad Interface

The EZ-KIT Lite features a 4 x 4 keypad assembly connected to the keypad interface of the ADSP-BF548 processor. The keypad connects to the EZ-KIT Lite via a nine-pin connector (P1). The keypad interface of the processor shares the same multi-function pins as the EPPI1 port and the host interface. Consequently, the same keypad pins connect to the host connector, PPI connector, and expansion interface. If you need to use the processor’s pins for functions other than keypad, simply disconnect the keypad via the eight-position keypad switch (SW2).

Rotary Encoder Interface

The ADSP-BF548 processor has a built-in, up-down counter with support for a rotary encoder. The three-wire rotary encoder interface connects to the rotary switch (SW3) and host connector. The rotary encoder can be turned clockwise for the up function, counter clockwise for the down function, or can be used as a push button for clearing the counter.

Ethernet Interface

The EZ-KIT Lite has a fully functional, high-performance, single-chip Ethernet controller with HP Auto-MDIX and is fully compliant with IEEE 802.2/802.2u standards. The SMSC LAN9218 chip contains an integrated Ethernet MAC and PHY, supports 10BASE-T and 100BASE-TX operations. The part is attached gluelessly to the ADSP-BF548 processor via the asynchronous memory bus and is mapped directly to the processor’s ~AMS1 memory bank. The IRQ signal of the Ethernet chip is mapped to the PE8 flag pin of the processor and is connected via the SW16 switch position 3. If PE8 needs to be used elsewhere on the board, turn off the SW16 switch to disconnect it from the Ethernet chip.

The Ethernet chip is pre-loaded with a valid IEEE MAC address for the EZ-KIT Lite. The MAC address is stored in the Ethernet serial ROM (U12) and can be found on a sticker on the bottom side of the EZ-KIT Lite. The serial ROM is connected directly to the LAN9218 and is accessed via the Ethernet chip only.

Audio Interface

The audio interface of the EZ-KIT Lite consists of an Analog Devices AD1980 audio codec and its associated passive components. The AD1980 is a AC’97 2.3 compliant SoundMAX codec that supports 5.1 surround sound. The codec carries integrated DACs and requires minimal external circuitry. The codec connects to the ADSP-BF548 processor via the processor’s serial port 0; the port is dedicated for the audio interface and does not connect to anything else on the board.

  • J10 can be used as a line or head phone out. J10 also can be configured via software as the front surround left and right channel or a 5.1 surround system.
  • J9 - The top location is the center channel on the left channel and the LFE out on the right channel. The bottom location of J9 is left and right back surround channels for a 5.1 surround system.
  • J8 has two locations for 3.5 mm cables. The top location is for a stereo microphone, and the bottom location is for a stereo line in.

ATAPI Interface

The ADSP-BF548 processor has a built-in advanced technology attachment packet interface (ATA/ATAPI-6) controller that can be attached to any peripherals that support ATAPI standards. The EZ-KIT Lite is shipped with a 2.5” Toshiba 5V 40GB ATAPI hard disk drive. The ATAPI interface shares pins with other peripherals on the EZ-KIT Lite. Consequently, the ATAPI interface of the processor can connect to an ATAPI device (hard drive) via the PPI port pins or the external address and data bus. The EZ-KIT Lite is wired such that it connects the ATAPI hard drive to the processor via the external address and data bus. Two external 5V tolerant bus switches (U4 and U24) are used between the 3.3V processor signals and the 5V ATPI hard drive. U24 connects to all control signals of the ATAPI controller and is always enabled. U4 connects to the 16-bit data bus of the processor and is enabled with simple signal conditioning:

  • When you write data to the hard drive, the FET switch U4 automatically connects the two devices together.
  • When you do not use the ATAPI interface, the FET switch U4 is disconnected, and the processor does not see the capacitive load or the net traces associated with the hard disk drive.

USB OTG Interface

The ADSP-BF548 processor has a built-in, high-speed USB on-the-go (OTG) interface and integrated PHY. This interface connects to a 24 MHz clock (U13), has surge protection, and can be configured as a host or device. When in device mode, the USB 5V regulator (VR1) and FET switch (U39) are turned OFF. When in host mode, the USB 5V regulator and FET are turned ON and can supply 5V at 500 mA.

The control mechanism to turn the two devices ON and OFF are via the PE7 flag pin of the processor. By default PE7 is set low or a logic ‘0’ via a pull-down resistor, and both devices are turned OFF.

UART Interface

The ADSP-BF548 processor has four built-in universal asynchronous receiver transmitters (UARTs). UART3–0 share the same processor pins as other peripherals on the EZ-KIT Lite. As a result, not all of the UARTs are available on the board: UART0 is not available on the board. UART1 has full RS-232 functionality via the Analog Devices 3.3V ADM3202 (U32) line driver and receiver. The UART can be disconnected from the ADM3202 bit by turning OFF all positions on the SW7 switch. If you are having troubles with the UART, check out if you are using the correct serial cable

CAN Interface

The Controller Area Network (CAN) interface contains two Philips TJA1041 high-speed CAN transceivers. The two transceivers are connected to the CAN0 and CAN1 ports of the processor. Either of the CAN ports can be used to transmit or receive data. The PC0 programmable flag connects to the error and power-on indication output of CAN0 (CAN0_ERR). The PC5 programmable flag connects to the error and power-on indication output of CAN1 (CAN1_ERR). The transmit and receive pins for both transceivers connect to the dedicated CAN0 and CAN1 transmit and receive pins of the processor.

Host Interface

The host DMA port of the Blackfin processor is available via a IDC 16×2 header (P3) on the EZ-KIT Lite. The port allows a host device external to the Blackfin processor to be a DMA master and transfer data back and forth.

RTC Interface

The ADSP-BF548 processor has a real-time clock (RTC) and a watchdog timer. Typically the RTC interface is used to implement a real-time watch or a life counter of the time elapsed since the last system reset. The EZ-KIT Lite is equipped with a Panasonic lithium coin 3V 24 MM battery with a 1000 mAh. The 3V battery and the 3.3V supply of the board are connected to the RTC power pin of the processor. When the EZ-KIT Lite is powered, it uses the board power to supply voltage to the RTC pin. When the EZ-KIT Lite is not powered, it uses the lithium battery to maintain the power to the RTC pin.

The battery allows you to evaluate the RTC functionality for the life of the EZ-KIT Lite. You can calculate your application’s specific power requirements and use a much smaller battery in a custom design.

LEDs and Push Buttons

The EZ-KIT Lite provides four push buttons and six LEDs for general-purpose I/O.

The six LEDs, labeled LED1 through LED6, are accessed via the PG6–11 pins of the processor.

The four general-purpose push button are labeled PB1 through PB4. The status of each individual button can be read through programmable flag (PF) inputs, PF8–11. A PF reads 1 when a corresponding switch is being pressed. When the switch is released, the PF reads 0.

Ethernet EEPROM Programming

If your board lacks a MAC address in the EEPROM attached to the SMSC LAN part, you can use the eeprom programmer with U-Boot (examples/smc911x_eeprom) to set one.

In the example below, we'll program the EEPROM to contain the address ae:11:21:ad:bb:89. Note that the first byte must be a5 according to the datasheet.

bfin> set ethaddr ae:11:21:ad:bb:89
bfin> tftp $(loadaddr) smc911x_eeprom
smc911x: initializing
smc911x: detected LAN9218 controller
smc911x: phy initialized
smc911x: MAC ae:11:21:ad:bb:89
TFTP from server; our IP address is
Filename 'smc911x_eeprom'.
Load address: 0x1000000
Loading: ##
Bytes transferred = 17970 (4632 hex)
bfin> bootelf
Loading phdr 0 to 0x00001000 (3284 bytes)
Loading phdr 1 to 0x00002cd4 (0 bytes)
## Starting application at 0x000011b0 ...

smc911x: detected LAN9218 controller

MAC/EEPROM Commands:
 P : Print the MAC addresses
 D : Dump the EEPROM contents
 M : Dump the MAC contents
 C : Copy the MAC address from the EEPROM to the MAC
 W : Write a register in the EEPROM or in the MAC
 Q : Quit

Some commands take arguments:
 W <E|M> <register> <value>
    E: EEPROM   M: MAC

eeprom> W E 0 A5
Writing EEPROM register 00 with a5
eeprom> W E 1 AE
Writing EEPROM register 01 with ae
eeprom> W E 2 11
Writing EEPROM register 02 with 11
eeprom> W E 3 21
Writing EEPROM register 03 with 21
eeprom> W E 4 AD
Writing EEPROM register 04 with ad
eeprom> W E 5 BB
Writing EEPROM register 05 with bb
eeprom> W E 6 89
Writing EEPROM register 06 with 89
eeprom> D
00: 0xa5
01: 0xae
02: 0x11
03: 0x21
04: 0xad
05: 0xbb
06: 0x89
eeprom> Q