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(Re)programming the CPLD on the BF533-STAMP

The routing of Programmable Flag pins PF0 to PF8 to/from the peripherals is taken care of by a Complex Programmable Logic Device (CPLD). The particular chip used is an ATF1504ASV. The default routing (see stamp_schematics_v1.2.pdf) is as follows:

From To
PF0,PF1 Bank Select
PF2 GUI_LED1
PF3 GUI_LED2
PF4 GUI_LED3
GUI_BUT1 PF5
GUI_BUT2 PF6
LAN_IRQ PF7
GUI_BUT3 PF8
RTS CTS

This particular pin assignment may not be suitable for every purpose. For example, the use of PF7 for LAN interrupt handling makes it impossible to use the PPI for >12 bit transfers, because PF7 is also connected to the 13th bit of the PPI bus. In that case, changing that particular assignment from PF7 to another pin (e.g. PF2) may be necessary.

The original CPLD program for the BF533-STAMP, which can be downloaded from stamp_cpld_v2.zip, has been created using Prochip Designer. This commercial program only has a 30 day trial period. Luckily, modification and re-programming of the CPLD program can be performed using the free WinCupl program and the free Atmel-ISP program. These programs can be downloaded from WinCupl page and Atmel-ISP page respectively.

Part 1: Mofifying the program

First, unzip (with full path) stamp_cpld_v2.zip to the root of C:, thus creating files in the C:\stamp_cpld_v2 directory. If you choose another folder, the WinCUPL program may give an error message.

Start WinCUPL and open C:\stamp_cpld_v2\code.PLD. You can modify and save the code. After modification, it has to be re-compiled. This can be done from inside WinCUPL or from the command-line:

Besides the main program (wincupl.exe), WinCUPL (5.30.4) contains two important command-line programs:

  • Wincupl\Shared\cupl.exe
  • Wincupl\WinCupl\Fitters\fit1504.exe

A device-dependent compile (key F9) from WinCupl creates a .JED (Jedec) file from the .PLD file by running these two programs in sequence:

FILENAME.PLD → CUPL.EXE → FILENAME.TT2 → FIT1504.EXE → FILENAME.JED

As a by-product, a file named FILENAME.FIT is created (amongst others). This filename is an extensive log file. You can use it to verify that the .JED file compilation has been performed using the right parameters.

The first method, compiling using WinCUPL itself, has one drawback: the outputs of a ATF15xx CPLD default to a slow slew-rate. The slew-rate can be tuned using a parameter called 'output_fast'. Unfortunately, there is no (reliable) way of passing this parameter to fit1504 from inside WinCupl. If you need this, you will have tp use the second method, using the tools directly from the command line. Whether your board needs some ports at a high slew-rate will probably depend on the clockspeed. If you are in doubt, just use the second method (or try the first and re-program again using the second if not satisfied).

Method 1: Compiling using WinCUPL

In WinCUPL, the device should be hand-selected to read “ATF1504AS TQPF44-ISP”, where the -ISP part of the name is very important. This is done in menu Options→ Devices (device type is TQFP). The box “Device in file” must not be checked. This overrides the “Device f1504tqfp44” setting in code.PLD.

When you compile (menu Run → Device Dependent Compile (F9) ), the compilation is performed with option ”-JTAG ON” instead of ”-JTAG OFF” because of the -ISP device type. This is important, because otherwise the JTAG port will be disabled after flashing the CPLD.

If you get no errors, you now have the code.JED file and the code.FIT file that you can open in notepad to verify the compilation.

Method 2: Compiling from the command-line

Assuming your command-line tools have been installed to C:\APL\Wincupl\Shared\cupl.exe and C:\APL\Wincupl\WinCupl\Fitters\fit1504.exe, the compilation is performed in two steps:

1. Running CUPL

C:\stamp_cpld_v2>c:\APL\Wincupl\Shared\cupl.exe -jxfu c:\APL\Wincupl\Shared\cupl.dl f1504isptqfp44 code.PLD

If you get no errors, you now have the code.TT2 file, which forms the input file for the next step. This .TT2 file is exactly the same as generated by WinCUPL, so you can skip this step if you have tried method 1 first.

2. Running FIT1504

C:\stamp_cpld_v2>c:\APL\Wincupl\WinCupl\Fitters\fit1504 code.tt2 -CUPL -dev P1504T44 -JTAG ON -output_fast PF8,PF7,PF6,PF5,GUI_LED3,GUI_LED2,GUI_LED1,FLASH_CS,FLASH_A20,FLASH_A19,EXP_AMS3,EXP_AMS2,EXP_AMS1,EXP_AMS0,ETHERNET_CS

If you get no errors, you now have the code.JED file and the code.FIT file to verify the compilation. The ”-output_fast” parameter, followed by a comma separated list (no spaces in between!) of all the outputs you want at a high slew-rate, is effectively the only difference between method 1 and method 2.

Part 2: Re-programming the CPLD

Start the Atmel ISP program and open the code.CHN file in the C:\stamp_cpld_v2 directory. If it is missing, it may have been deleted by WinCUPL: just get it back from the original ZIP file.

Make sure the Port setting (e.g. LPT1) and cable type (e.g. Atmel ISP) is set correctly and the STAMP is connected using its J5 (CPLD JTAG) connector. Press Run to program/verify the CPLD.

If Atmel-ISP refuses to program DO NOT click “JTAG Port Check Override”. If you override this check, you may disable the JTAG port, making subsequent re-programming impossible.

If you want to do a non-destructive test first, doubleclick on the text inside the “Chain File Hierarchy”, change the “Jtag instruction” from “Program/Verify” to “Load” and type another name in the “Jedec file” field. When you run the program now, it reads the CPLD and creates the a .JED file with the name you specified. If you perform multiple reads, a program like 'diff' will reveal any differences - only the timestamp should be different. If each read creates a different .JED file, the JTAG cable may be too long, creating errors.