world leader in high performance signal processing
Trace: » bf533-ezkit

BF533-EZkit

www.analog.com_static_imported-files_images_product_descriptions_38092608585777137873875bf533_hardware.jpg

The Blackfin Linux developers do not typically develop on or use the BF533-EZKIT. If you use this platform, you may run into issues. The following information is provided as a service, but is not meant to be an authoritative guide on the subject. There are third party BF533 development systems that are recommended, which you can find in the buy_stuff section.

Known limitations:

  • flash is too small to put a default uImage in. You can remove files until this is small enough.

The complete BF533-EZKit manual is available on the ADI Web site. This section are select sections from that manual (copied with permission).

Board Description

The EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-BF533 Blackfin processor. The processor has IO voltage of 3.3V. The core voltage is derived from this 3.3v supply and uses the internal regulator of the processor. The core voltage and the core clock rate can be set on the fly by the processor. Refer to the Hardware Reference Manual for more information.

The External Bus Interface Unit (EBIU) connects an external memory to the ADSP-BF533 device. It includes a 16-bit wide data bus, an address bus, and a control bus. Both 16-bit and 8-bit access are supported. On the EZ-KIT Lite, the EBI unit connects to SDRAM and flash memory. 64 MB (32M x 16 bits) of SDRAM connect to the synchronous memory select 0 pin (~SMS0). Refer to “SDRAM Interface” on page 1-7 for information about configuring the SDRAM. Note that SDRAM clock is the processor’s Clock Out (CLK OUT), which frequency should not exceed 133 MHz.

Two flash memory devices are connected to the asynchronous memory select signals, ~AMS2 through ~AMS0. The devices provide total of 2 Mbytes of primary flash memory, 128 Kbytes of secondary flash memory, and 64 Kbytes of SRAM. The processor can use this memory for both booting and storing information during normal operation.

Board Revisions

The U-Boot and the Linux kernel should work on just about any board revision. These versions have been explicitly tested:

Silicon Rev Board Rev
BF533-0.3 Rev 1.7
BF533-0.5 Rev 2.1

On Board peripherals

The on-board audio and video is not expected to work under Linux.

Jumper and Switch Settings

Please make sure the following switch settings are in place for the Ez-kit and the Ez-extender card.

BF533-EZKit

UART Loop Jumper (JP4)

The UART loop jumper (JP4) allows the loop back connection of transmit and receive signals. The correct position for uClinux is the OFF position. If you are having troubles with the UART, check out if you are using the correct serial cable

Boot Mode Switch (SW11)

Positions 1 and 2 of SW11 set the boot mode of the processor. On older versions of the board, these were JP1 and JP2 jumpers. The table shows the available boot mode settings. By default, the processor boots from the on-board flash memory (XIP). Normally U-Boot expects both switches/jumpers to be on/installed. Please check with the bootrom supports, for more info on supported booting methods.

SW11.1 / JP1 (BMODE1) SW11.2 / JP2 (BMODE0) Boot Mode
Installed Installed 16-Bit External Memory (XIP)
Installed Not installed Flash Memory (LDR)
Not installed Installed SPI host slave
Not installed Not installed SPI EEPROM (LDR)

Test DIP Switches (SW1 and SW2)

Two DIP switches (SW1 and SW2) are located on the bottom of the board. The switches are used only for testing and should be in the OFF position.

Video Configuration Switch (SW3)

The video configuration switch (SW3) controls how some video signals from the ADV7183 video decoder and ADV7171 video encoder are routed to the processor’s PPI. uClinux does not support the ADV7183 video decoder or the ADV7171 on the EZ-Kit.

Push Button Enable Switch (SW9)

The push button enable (SW9) switch positions 1 through 4 disconnect the drivers associated with the push buttons from the PF pins of the processor. Positions 5 and 6 are used to connect the transmit and receive frame syncs and clocks of SPORT0.

Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2)
1 ON 1 SW4 12 PF8
2 ON 2 SW5 11 PF9
3 ON 3 SW6 10 PF10
4 ON 4 SW7 9 PF11
5 OFF 5 TFS0 8 RFS0
6 OFF 6 RSCLK0 7 TSCLK0

SPIS1/SPISS Select Switch (SW10)

The SPIS1/SPISS select switch (SW10) disconnects the SPIS1 and SPISS signals from the board, making them available on the SPI connector (P6).

SPORT0 Switch (SW12)

When is set to OFF, SW12 disconnects SPORT0 from the audio codec. The switch is used when SPORT0 signals are desired at the expansion interface.

USB-LAN EZ-Extender

See the USB-LAN EZ-Extender page for more information.

Power Select Jumper (JP1)

The power select jumper, JP1, by default, must have no jumpers on any of its pins.

LAN Power Jumper (JP2)

The LAN power jumper, JP2, is used to power the SMSC’s 91C111 device with 3.3V. By default, and, in general, the jumper is plugged in.

Link Jumper (JP3)

The link jumper, JP3, of the USB-LAN EZ-Extender directly connects to the link status pin of the SMSC’s 91C111 device. The default setting is to keep the link jumper unpopulated.

ADDR Enable Switch (SW1.1)

The address enable switch, SW1.1, is used to control the output of the Blackfin address bus buffer. By default, the switch is set to the ON position. If in the OFF position, the user cannot communicate to the USB or the Ethernet processor.

FLAGS Enable Switch (SW1.2)

The flags enable switch, SW1.2, is used to control the output of the Blackfin Flags multiplexer. By default, the SW1.2 switch is set to the ON position. If is in the OFF position, the user cannot communicate to the USB or Ethernet processor.

USB IRQ Enable Switch (SW1.3)

The USB IRQ enable switch, SW1.3, is used to control the connection between the Netchip 2272 IRQ line with the respective flag pin on the Blackfin processor.

Test Mode Enable Switch (SW1.4)

The test mode enable switch, SW1.4, is an internal test pin and should not be used. This switch, by default, is set to the OFF position.

Serial ROM Enable Switch (SW2.1)

The serial ROM enable switch, SW2.1, is used to control the connection between the LAN91C111 Ethernet processor with its serial ROM (U3). When the switch is disabled, the Ethernet processor loads its Media Access Control (MAC) address from the serial ROM. The SW2.1 switch, by default, is set to the OFF position.

IOS[2:0] Switch (SW2.2, SW2.3, SW2.4)

The IOS[2:0] bits on the USB-LAN EZ-Extender are directly connected to the IOS[2:0] pins of the LAN91C111 Ethernet processor. These switches, by default, are set to the OFF positions.

Switch Summary

BF533-EZKit

USB-LAN

Other Cards

Do not use the BF533-EZKIt with other extender cards, and expect them to work with Linux (even boot) - we don't test them, and don't have them to validate things on.