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Blackfin Boot ROM

All Blackfin processors have an on-chip boot ROM that has the ability to boot from a wide variety of sources. The files it boots are in a special format normally referred to as an LDR. Different versions of Blackfins have different boot modes (commonly shortened as “BMODEs”), so you should consult the datasheet for your variant to see exactly what options are available.

Boot Modes

All boot modes expect the executable file to be in an LDR format. The two exceptions to this are the “Idle” mode (since nothing is actually executed) and the “Bypass” mode (which is not available on all Blackfin variants).

Keep in mind that while the internal Blackfin processor group validates all boot modes work from the silicon point of view, not all modes are normally tested in conjunction with the open source bootloaders. While they should of course all work, we will enumerate the ones known to work (and thus are regularly tested).

Tested Boot Mode Description File Format
No boot / IDLE Do not boot, just execute the IDLE instruction. Useful to recover via JTAG. none
Bypass Boot ROM Jump to first async bank at 0x20000000 and start executing instructions. Binary
Flash Boot from 8bit/16bit flash memory attached to first async bank at 0x20000000. LDR
SPI Boot from a SPI serial flash. LDR
SPI Slave External device loads code via SPI. LDR
I2C Boot from an I2C serial flash. LDR
I2C Slave External device loads code via I2C. LDR
UART External device loads code via UART. LDR
RAM Perform a “warm boot” from external RAM. Binary
OTP Boot from on-chip One-Time-Programmable memory. LDR
NAND Boot from a NAND flash. LDR
FIFO External device loads code via FIFO. LDR
Host DMA External device loads code via DMA. LDR

Details

  • Execute from 16-bit external memory – Execution starts from address 0x20000000 with 16-bit packing. The boot-ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).
  • Boot from 8-bit and 16-bit external flash memory – The 8-bit or 16-bit flash boot routine located in boot ROM memory space is set up using Asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). The boot ROM evaluates the first byte of the boot stream at address 0x20000000. If it is 0×40, 8-bit boot is performed. A 0×60 byte is required for 16-bit boot.
  • Boot from serial SPI memory (EEPROM or flash). 8-,16-, or 24-bit addressable devices, and SPI dataflash are supported.
    • Standard 8-, 16-, and 24-bit addressable SPI memories are defined as memories that take in a read command byte of 0x03 followed by:
      • one address byte (for 8-bit addressable SPI memories),
      • two address bytes (for 16-bit addressable SPI memories),
      • or three address bytes (for 24-bit addressable SPI memories).
    • After the correct read command and address are sent, the data stored in the memory at the selected address is shifted out on the MISO pin. Data is sent out sequentially from that address with continuing clock pulses.
    • Data flash devices are compatible with the AT45DB321, AT45DB041, AT45DB081, or AT45DB161 from Atmel.
    • Check the Blackfin datasheet to determine which PF output pin is used as a chip select a for the SPI EEPROM/flash device.
  • Boot from SPI host device – The Blackfin processor operates in SPI slave mode and is configured to receive the bytes of the .LDR file from an SPI host (master) agent. To hold off the host device from transmitting while the boot ROM is busy, the Blackfin processor will assert a flag pin to signal the host device not to send any more bytes until the flag is de-asserted. The flag is chosen by the user and this information will be transferred to the Blackfin processor via bits 8:5 of the FLAG header.
  • Boot from UART – Using an autobaud handshake sequence, a boot-stream-formatted program is downloaded by the Host. The Host agent selects a baud rate within the UART's clocking capabilities. When performing the autobaud, the UART expects a “@” (boot stream) character (eight bits data, one start bit, one stop bit, no parity bit) on the RXD pin to determine the bit rate. It then replies with an acknowledgment which is composed of 4 bytes: 0xBF, the value of UART_DLL, the value of UART_DLH, 0×00. The Host can then download the boot stream. When the processor needs to hold off the Host, it de-asserts CTS. Therefore, the Host must monitor this signal.
  • Boot from serial I2C memory (EEPROM/flash) – The Blackfin processor operates in master mode and selects the TWI slave with the unique id 0xA0. It submits successive read commands to the memory device starting at two byte internal address 0×0000 and begins clocking data into the processor. The TWI memory device should comply with Philips I2C Bus Specification version 2.1 and have the capability to auto-increment its internal address counter such that the contents of the memory device can be read sequentially.
  • Boot from I2C Host – The TWI Host agent selects the slave with the unique id 0x5F. The processor replies with an acknowledgment and the Host can then download the boot stream. The TWI Host agent should comply with Philips I2C Bus Specification version 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI.

NAND Considerations

Some special considerations need to be made if you wish to boot directly from NAND on newer processors (such as the BF54x). The Blackfin on-chip Boot ROM expects a different ECC/bad block layout in the spare area than the one typically used by U-Boot or Linux.

All bits in the bad block marker must be 1, otherwise the page is considered bad.

The legend for the below map is:

Key Meaning
BB bad block marker
NA does not matter; ignored
EC ECC byte (used in groups of 3)

By default, the layout commonly used looks like:

00: BB NA NA NA NA NA NA NA
08: NA NA NA NA NA NA NA NA
10: NA NA NA NA NA NA NA NA
18: NA NA NA NA NA NA NA NA
20: NA NA NA NA NA NA NA NA
28: EC EC EC EC EC EC EC EC
30: EC EC EC EC EC EC EC EC
38: EC EC EC EC EC EC EC EC

The Blackfin Boot ROM however requires this layout:

00: EC EC EC NA NA NA NA NA
08: EC EC EC NA NA NA NA NA
10: EC EC EC NA NA NA NA NA
18: EC EC EC NA NA NA NA NA
20: EC EC EC NA NA NA NA NA
28: EC EC EC NA NA NA NA NA
30: EC EC EC NA NA NA NA NA
38: EC EC EC NA NA NA NA BB

Availability

We will not document the actual binding between the BMODE pins and the processor variant. Consult the datasheet if you need that information. Also be aware that some modes may not be available on all versions of silicon for a particular family. Again, consult the datasheet for your silicon revision.

Mode BF52x BF53[123] BF53[467] BF53[89] BF54x BF561
IDLE
Bypass
Flash
SPI
SPI Slave
I2C
I2C Slave
UART
RAM
OTP
NAND
FIFO
Host DMA

Memory Locations

The Boot ROM is typically mapped read-only into the Blackfin address space at 0xEF000000. This should be readable by anyone, user mode or supervisor mode. While older versions did not have callable functions, newer ones do. Not all functions are restricted to booting and in fact, can and should be used at runtime.

The Blackfin headers provide defines for these values as well as C prototypes. Note that the define macros are all prefixed with _BOOTROM_. So when we list SPIBOOT below, you want to use the define _BOOTROM_SPIBOOT.

For indepth information on these functions, consult the System Reset and Booting chapter of the HRM.

Function Address Description
RESET 0xEF000000 Starting address at reset
FINAL_INIT 0xEF000002 Jump to the address in EVT1
PDMA 0xEF000004 Load LDR block via peripheral DMA
MDMA 0xEF000006 Load LDR block via memory DMA
MEMBOOT 0xEF000008 Boot LDR out of memory
TWIBOOT 0xEF00000C Boot LDR from I2C
SPIBOOT 0xEF00000A Boot LDR from SPI
/* reserved */ 0xEF00000E
GET_DXE_ADDRESS_FLASH 0xEF000010 Legacy: fetch address from Flash
GET_DXE_ADDRESS_SPI 0xEF000012 Legacy: fetch address from SPI
GET_DXE_ADDRESS_TWI 0xEF000014 Legacy: fetch address from I2C
/* reserved */ 0xEF000016
OTP_CONTROL 0xEF000018 Init and manage OTP memory
OTP_READ 0xEF00001A Read OTP memory
OTP_WRITE 0xEF00001C Write OTP memory
ECC_TABLE 0xEF00001E
BOOTKERNEL 0xEF000020 Internal entry point for boot kernel
GETPORT 0xEF000022
NMI 0xEF000024 Default NMI handler
HWERROR 0xEF000026 Default hardware error handler
EXCEPTION 0xEF000028 Default exception handler
CRC32 0xEF000030 Calc CRC32 on a region of memory
CRC32POLY 0xEF000032 Generate lookup table from CRC32 poly
CRC32CALLBACK 0xEF000034 Callback entry point for CRC32
CRC32INITCODE 0xEF000036 Initialize CRC32 routines
SYSCONTROL 0xEF000038 Power and reset management
VERSION 0xEF000040 Bootrom version information

Source Code

The source code for the Boot ROM is usually bundled with Visual DSP. Since that'd be mean to force you to get Visual DSP, you can find copies here.