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Trace: » unaligned_accesses

Unaligned Accesses

Any of the following instructions can cause a unaligned exception

Opcode range Instruction
0x8000 - 0x81FF Dreg = [ Preg++ Preg]
0x8200 - 0x83FF Dreg_lo = W[Preg]
0x8201 - 0x83FE Dreg_lo = W[Preg ++ Preg]
0x8400 - 0x85FF Dreg_hi = W[Preg]
0x8401 - 0x85FE Dreg_hi = W[Preg ++ Preg]
0x8601 - 0x87FE Dreg = W[Preg ++ Preg](Z)
0x8E00 - 0x8FFF Dreg = W[Preg ++ Preg](X)
0x9000 - 0x903F Dreg = [ Preg ++ ]
0x9040 - 0x907F Preg = [Preg++]
0x9080 - 0x90BF Dreg = [Preg––]
0x90C0 - 0x90FF Preg = [Preg––]
0x9100 - 0x913F Dreg = [Preg ]
0x9200 - 0x923F [Preg++] = Dreg
0x9240 - 0x927F [Preg++] = Preg
0x92C0 - 0x92FF [Preg––] = Preg
0x9300 - 0x933F [Preg] = Dreg
0x9340 - 0x937F [Preg] = Preg
0x9400 - 0x943F Dreg = W[Preg++](Z)
0x9440 - 0x947F Dreg = W[Preg++](X)
0x9480 - 0x94BF Dreg = W[Preg––](Z)
0x94C0 - 0x94FF Dreg = W[Preg––](X)
0x9500 - 0x953F Dreg = W[Preg](Z)
0x9540 - 0x957F Dreg = W[Preg](X)
0x9C00 - 0x9C1F Dreg = [Ireg++]
0x9C20 - 0x9C3F Dreg_lo = W[Ireg++]
0x9C40 - 0x9C5F Dreg_hi = W[Ireg++]
0x9C80 - 0x9C9F Dreg = [Ireg––]
0x9CA0 - 0x9CBF Dreg_lo = W[Ireg––]
0x9CC0 - 0x9CDF Dreg_hi = W[Ireg––]
0x9D00 - 0x9D1F Dreg = [Ireg]
0x9D20 - 0x9D3F Dreg_lo = W[Ireg]
0x9D40 - 0x9D5F Dreg_hi = W[Ireg]
0x9D80 - 0x9DFF Dreg = [Ireg ++ Mreg]
0x9F80 - 0x9FFF [Ireg ++ Mreg ] = Dreg
0xA000 - 0xA3FF Dreg = [Preg + uimm6m4]
0xA400 - 0xA7FF Dreg = W[Preg + uimm5m2](Z)
0xA800 - 0xABFF Dreg = W[Preg + uimm5m2](X)
0xAC00 - 0xAFFF Preg = [Preg + uimm6m4]
0xB800 - 0xB9F7 Dreg = [FP – uimm7m4]
0xB808 - 0xB9FF Preg = [FP – uimm7m4]
0xBA08 - 0xBBFF [FP – uimm7m4] = Preg
0xBC00E700 - 0xBFFFE7EF [Preg + uimm6m4] = Preg
0xE4000000 - 0xE4EF7FFF Dreg = [ Preg + uimm6m4 ]
0xE4400000 - 0xE47F8FFF Dreg = W[Preg + uimm16m2](Z)
0xE4408000 - 0xE47FFFFF Dreg = W[Preg – uimm17m4](Z)
0xE5000000 - 0xE53F7FFF Preg = [Preg + uimm17m4]
0xE5008000 - 0xE53FFFFF Preg = [Preg – uimm17m4]
0xE5400000 - 0xE57F8FFF Dreg = W[Preg + uimm16m2](X)
0xE5408000 - 0xE57FFFFF Dreg = W[Preg – uimm16m2](X)
0xE7000000 - 0xE73F8FFF [Preg + uimm17m4] = Preg
0xE7008000 - 0xE73FFFFF [Preg – uimm17m4] = Preg

It would be possible, when the processor receives a unaligned exception in the kernel, to disassemble the offending instruction, determine what registers/offsets are being used, and use byte instructions to emulate the load. However, this would take a long time - code would work, but it would be very slow.

Things are also made more complex by parallel instructions. Any of the 16-bit instructions can be put in parallel with many other instructions. This makes it much more difficult to emulate - as all the non load/store instructions are required to be emulated as well. For example, a parallel instruction is the combination of a 32-bit ALU/MAC instruction, and two 16-bit instructions (normally a load/store instructions). For example saa (r1:0, r3:2) || r0=[i0++] || r2=[i1++] ; is a valid parallel instruction. In order to handle unaligned accesses, the entire instruction would be decoded, and both the loads would be emulated. There can be more complex examples - r7.h=r7.l=sign(r2.h)*r3.h + sign(r2.l)*r3.l || i0+=m3 || r0=[i0] ; Since both the 16-bit instructions are operating on the same register, special care must be taken to emulate these as the core does while it is running normally - you can not emulate them from right to left, or you will calculate the incorrect results.

It is for these reasons (things would run slow, and to have 100% coverage, it would be really difficult), that we have decided not to do this. If you want to - let us know and we can review your patch.