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Supervisor Mode

The processor services all interrupt, NMI, and exception events in Supervisor mode.

Supervisor mode has full, unrestricted access to all processor system resources, including all emulation resources, unless a CPLB has been con- figured and enabled. See “Memory Management Unit” on page 6-45 for a further description. Only Supervisor mode can use the register alias USP, which references the User Stack Pointer in memory. This register alias is necessary because in Supervisor mode, SP refers to the kernel stack pointer rather than to the user stack pointer.

Normal processing begins in Supervisor mode from the Reset state. Deasserting the RESET signal switches the processor from the Reset state to Supervisor mode where it remains until an emulation event or Return instruction occurs to change the mode. Before the Return instruction is issued, the RETI register must be loaded with a valid return address.

Non-OS Environments

For non-OS environments, application code should remain in Supervisor mode so that it can access all core and system resources. When RESET is deasserted, the processor initiates operation by servicing the reset event. Emulation is the only event that can pre-empt this activity. Therefore, lower priority events cannot be processed.

One way of keeping the processor in Supervisor mode and still allowing lower priority events to be processed is to set up and force the lowest priority interrupt (IVG15). Events and interrupts are described further in “Events and Interrupts” on page 4-29. After the low priority interrupt has been forced using the RAISE 15 instruction, RETI can be loaded with a return address that points to user code that can execute until IVG15 is issued. After RETI has been loaded, the RTI instruction can be issued to return from the reset event.

The interrupt handler for IVG15 can be set to jump to the application code starting address. An additional RTI is not required. As a result, the processor remains in Supervisor mode because IPEND[15] remains set. At this point, the processor is servicing the lowest priority interrupt. This ensures that higher priority interrupts can be processed.

To remain in Supervisor mode when coming out of the Reset state, use code as shown:

    P0.L = LO(EVT15) ;    /* Point to IVG15 in Event Vector Table */
    P0.H = HI(EVT15) ;
    P1.L = START ;        /* Point to start of User code */
    P1.H = START ;
    [P0] = P1 ;           /* Place the address of start code in IVG15 of EVT */
    P0.L = LO(IMASK) ;
    R0 = [P0] ;
    R1.L = LO(EVT_IVG15) ;
    R0 = R0 | R1 ;
    [P0] = R0 ;           /* Set (enable) IVG15 bit in Interrupt Mask Register */

    RAISE 15 ;            /* Invoke IVG15 interrupt */
    P0.L = WAIT_HERE ;
    P0.H = WAIT_HERE ;
    RETI = P0 ;           /* RETI loaded with return address */
    RTI ;                 /* Return from Reset Event */

WAIT_HERE :           /* Wait here till IVG15 interrupt is serviced */

START:   /* IVG15 vectors here */
    [--SP] = RETI ;   /* Enables interrupts and saves return address to stack */