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Reset State

Reset state initializes the processor logic. During Reset state, application programs and the operating system do not execute. Clocks are stopped while in Reset state.

The processor remains in the Reset state as long as external logic asserts the external RESET signal. Upon deassertion, the processor completes the reset sequence and switches to Supervisor mode, where it executes code found at the reset event vector.

Software in Supervisor or Emulation mode can invoke the Reset state without involving the external RESET signal. This can be done by issuing the Reset version of the RAISE instruction.

Application programs in User mode cannot invoke the Reset state, except through a system call provided by an operating system kernel. The table below summarizes the state of the processor upon reset:

Item Description of Reset State
Core
Operating Mode Supervisor mode in reset event, clocks stopped
Rounding Mode Unbiased rounding
Cycle Counters Disabled, zero
DAG Registers (I, L, B, M) Random values (must be cleared at initialization)
Data and Address Registers Random values (must be cleared at initialization)
IPEND, IMASK, ILAT Cleared, interrupts globally disabled with IPEND bit 4
CPLBs Disabled
L1 Instruction Memory SRAM (cache disabled)
L1 Data Memory SRAM (cache disabled)
Cache Validity Bits Invalid
System
Booting Methods Determined by the values of BMODE pins at reset
MSEL Clock Frequency Reset value = 10
PLL Bypass Mode Disabled
VCO/Core Clock Ratio Reset value = 1
VCO/System Clock Ratio Reset value = 5
Peripheral Clocks Disabled

System Reset and Powerup

The Table below describes the five types of resets.

all resets, except System Software, reset the core.

Table 3-6. Resets

Reset Source Result
Hardware Reset The RESET pin causes a hardware reset Result Resets both the core and the peripherals, including the Dynamic Power Management Controller (DPMC). Resets the No Boot on Software Reset bit in SYSCR. For more information, see “SYSCR Register” on page 3-14.
System Software Reset Writing b#111 to bits [2:0] in the system MMR SWRST causes a System Software reset Resets only the peripherals, excluding the RTC (Real-Time Clock) block and most of the DPMC. The DPMC resets only the No Boot on Software Reset bit in SYSCR. Does not reset the core. Does not initiate a boot sequence.
Watchdog Timer Reset Programming the watchdog Resets both the core and the peripherals, excluding the RTC block and most of the DPMC. The Software Reset register (SWRST) can be read to determine whether the reset source was the watchdog timer
Core Double Fault Reset If the core enters a double-fault state, a reset can be caused by unmasking the Core Double Fault Reset Mask bit in the System Interrupt Controller Interrupt Mask register (SIC_IMASK). Result Resets both the core and the peripherals, excluding the RTC block and most of the DPMC. The SWRST register can be read to determine whether the reset source was Core Double Fault.
Core-Only Software Reset This reset is caused by executing a RAISE1 instruction or by setting the Software Reset (SYSRST) bit in the core Debug Control register (DBGCTL) via emulation software through the JTAG port. The DBGCTL register is not visible to the memory map. Resets only the core. The peripherals do not recognize this reset.

Hardware Reset

The processor chip reset is an asynchronous reset event. The RESET input pin must be deasserted to perform a hardware reset. For more information, see the product data sheet.

A hardware-initiated reset results in a system-wide reset that includes both core and peripherals. After the RESET pin is deasserted, the processor ensures that all asynchronous peripherals have recognized and completed a reset. After the reset, the processor transitions into the Boot mode sequence configured by the BMODE state.

The BMODE pins are dedicated mode control pins. No other functions are shared with these pins, and they may be permanently strapped by tying them directly to either VDD or VSS. The pins and the corresponding bits in SYSCR configure the Boot mode that is employed after hardware reset or System Software reset. See “Reset Interrupt” on page 4-46, and Table 4-11, “Events That Cause Exceptions,” on page 4-63 for further information.

SYSCR Register

The values sensed from the BMODE pins are latched into the System Reset Configuration register (SYSCR) upon the deassertion of the RESET pin. The values are made available for software access and modification after the hardware reset sequence. Software can modify only the No Boot on Software Reset bit.

The various configuration parameters are distributed to the appropriate destinations from SYSCR. Refer to the Reset and Booting chapter of your Blackfin Processor Hardware Reference for details.

Software Resets and Watchdog Timer

A software reset may be initiated in three ways:

  • By the watchdog timer, if appropriately configured
  • By setting the System Software Reset field in the Software Reset register (see Figure 3-2 on page 3-16)
  • By the RAISE1 instruction

The watchdog timer resets both the core and the peripherals. A System Software reset results in a reset of the peripherals without resetting the core and without initiating a booting sequence.

The System Software reset must be performed while executing from Level 1 memory (either as cache or as SRAM).

When L1 instruction memory is configured as cache, make sure the System Software reset sequence has been read into the cache.

After either the watchdog or System Software reset is initiated, the proces- sor ensures that all asynchronous peripherals have recognized and completed a reset.

For a reset generated by the watchdog timer, the processors transitions into the Boot mode sequence. The Boot mode is configured by the state of the BMODE and the No Boot on Software Reset control bits. If the No Boot on Software Reset bit in SYSCR is cleared, the reset sequence is determined by the BMODE control bits.

SWRST Register

A software reset can be initiated by setting the System Software Reset field in the Software Reset register (SWRST). Bit 15 indicates whether a software reset has occurred since the last time SWRST was read. Bit 14 and Bit 13, respectively, indicate whether the Software Watchdog Timer or a Core Double Fault has generated a software reset. Bits [15:13] are read-only and cleared when the register is read. Bits [3:0] are read/write.

When the BMODE pins are not set to b#00 and the No Boot on Software Reset bit in SYSCR is set, the processor starts executing from the start of on-chip L1 memory. In this configuration, the core begins fetching instructions from the beginning of on-chip L1 memory.

When the BMODE pins are set to b#00 the core begins fetching instructions from address 0x2000 0000 (the beginning of ASYNC Bank 0).

Core-Only Software Reset

A Core-Only Software reset is initiated by executing the RAISE 1 instruction or by setting the Software Reset (SYSRST) bit in the core Debug Control register (DBGCTL) via emulation software through the JTAG port. (DBGCTL is not visible to the memory map.)

A Core-Only Software reset affects only the state of the core. Note the system resources may be in an undetermined or even unreliable state, depending on the system activity during the reset period.

Core and System Reset

To perform a system and core reset, use the code sequence shown:

    /* Issue soft reset */
    P0.L = LO(SWRST) ;
    P0.H = HI(SWRST) ;
    R0.L = 0x0007 ;
    W[P0] = R0 ;
    SSYNC ;
    /* Clear soft reset */
    P0.L = LO(SWRST) ;
    P0.H = HI(SWRST) ;
    R0.L = 0x0000 ;
    W[P0] = R0 ;
    SSYNC ;
    /* Core reset - forces reboot */
    RAISE 1 ;