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Understanding JTAG

The JTAG standard defines circuitry that may be built to assist in the test, maintenance, and support of assembled printed circuit boards. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a Boundary-Scan register, such that the component can respond to a minimum set of instructions designed to help test printed circuit boards. The standard defines test logic that can be included in an integrated circuit to provide standardized approaches to:

  • Testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board
  • Testing the integrated circuit itself
  • Observing or modifying circuit activity during normal component operation (debugging)

The JTAG section is split up into:

ADI Interface

All boards that come from ADI use the same physical connection. The JTAG debuggers interface with the processor using a 14-pin JTAG header. The header provides a connection interface for the JTAG emulator pods. The header can also be used to route an optional local boundary scan controller to the DSP when the JTAG pod is not attached.

Information on functional, electrical, and mechanical requirements for interfacing a target with a JTAG pod can be found in ADI's EE Note #68. Do not use older versions of EE-68 for new target designs. Periodically check ADI’s web site for newer revisions of this document.

JTAG pods use a super set of the IEEE 1149.1 standard to send and receive data from the processor JTAG emulation port. The JTAG pod sometimes use an additional signal called EMU~ as a emulation status flag from the processor. This signal is a vendor specific signal, which is not part of the IEEE 1149.1 specification.

See this list of JTAG devices which are known to work with this interface.