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Trace: » instruction_modes

This table documents the instruction modes

Example Default FU IS IU T TFU S2RND ISS2 IH W32
Accumulator to Half D-register Moves R0.L = A0 (FU); V V V V V V/ND V V V E
Accumulator to D-register Moves R0 = A0 (FU); V V V/ND V/ND E E V V E E
Multiply 16-Bit Operands to Half Dreg R0.H = R1.L * R2.H (FU); V V V V V V V V V E
Multiply 16-Bit Operands to Dreg R0 = R1.L * R2.H (FU); V V V E E E V/ND V E E
Multiply and Multiply-Accumulate to Accumulator A0 = R1.L * R2.H (FU); V V V E E E E E E V
Multiply and Multiply-Accumulate to Half-Register R0.L = (A0 = R1.L * R2.H) (FU); V V V V V V V V V E
Multiply and Multiply-Accumulate to Data Register R0 = (A0 = R1.L * R2.H) (FU); V V V V/ND E E V V E E
V Supported by VDSP and in document*
V/ND Supported by VDSP and but Not in Document*
E Error, invalid mode

* ADSP-BF53x/BF56x Blackfin Processor Programming Reference (Revision 1.2, February 2007)