Table of Contents

Anomalies which effect the System

There are some anomalies which can no software workaround possible. You are responsible for ensuring that proper system and hardware design takes care of these issues. You should review the Anomaly List to see if these issues effect the parts you are working on.

05000207

Description

When a “brown-out” occurs, the internal Voltage regulator cannot be reset using the hardware reset pin. A “brown-out” is defined as a condition in which VDDext drops below the range specified in the data sheet, but does not drop all the way to 0 V, before it returns to the proper value.

Workaround

In order to recover from a “brown-out”, the processor must be powered down completely (VDD to ground) and then powered back up.

05000219

Description

If the NMI pin is asserted at boot time, the boot process will fail because there is no handler in the boot ROM. The behavior is not predictable.

Workaround

Do not assert the NMI pin during a boot sequence.

05000231

Description

The STB bit controls how many stop-bits are generated by the transmitter.

However, this setting also incorrectly affects how many stop-bits are sampled by the receiver. The correct behavior is for the receiver to always sample and test one stop-bit. However, the receiver will sample and test the number of stop-bits set by the STB bit. This incorrect behavior also affects framing error detection.

Workaround

None

If you are going to set the Blackfin device to for 2 stop bits - make sure that the device on the other end is also sending 2 stop bits.

05000265

Description

A noisy board environment combined with slow input edge rates on external SPORT receive (RSCLK) and transmit clocks (TSCLK) may cause a variety of observable problems. Unexpected high frequency transitions on the RSCLK/TSCLK can cause the SPORT to recognize an extra noise-induced glitch clock pulse.

The high frequency transitions on the RSCLK/TSCLK are most likely to be caused by noise on the rising or falling edge of external serial clocks. This noise, coupled with a slowly transitioning serial clock signal, can cause an additional bit-clock with a short period due to high sensitivity of the clock input. A slow slew rate input allows any noise on the clock input around the switching point to cause the clock input to cross and re-cross the switching point. This oscillation can cause a glitch clock pulse in the internal logic of the serial port.

Problems which may be observed due to this glitch clock pulse are:

In Stereo Serial mode (bit 9 set in SPORTx_RCR2), unexpected high frequency transitions on RSCLK/TSCLK can cause the SPORT to miss rising or falling edges of the word clock. This causes left or right words of Stereo Serial data to be lost. This may be observed as a Left/Right channel swap when listening to stereo audio signals. The additional noise-induced bit-clock pulse on the SPORT's internal logic results in the FS edge-detection logic generating a pulse with a smaller width and, at the same time, prevents the SPORT from detecting the external FS signal during the next ‘normal' bit-clock period. The FS pulse with smaller width, which is the output of the edge-detection logic, is ignored by the SPORT's sequential logic. Due to the fact that the edge detection part of the FS-logic was already ‘triggered', the next ‘normal' RSCLK will not detect the change in RFS anymore. In I2S/EIAJ mode, this results in one stereo sample being detected/transferred as two left/right channels, and all subsequent channels will be word-swapped in memory.

In multichannel mode, the mutlichannel frame delay (MFD) logic receives the extra sync pulse and begins counting early or double counting (if the count has already begun). A MFD of zero can roll over to 15, as the count begins one cycle early.

In early frame sync mode, if the noise occurs on the driving edge of the clock the same cycle that FS becomes active, the FS logic receives the extra runt pulse and begins counting the word length one cycle early. The first bit will be sampled twice and the last bit will be skipped.

In all modes, if the noise occurs in any cycle after the FS becomes active, the bit counting logic receives the extra runt pulse and advances too rapidly. If this occurs once during a work unit, it will finish counting the word length one cycle early. The bit where the noise occurs will be sampled twice, and the last bit will be skipped.

Workaround

Deal with it on the printed circuit board.

  1. Decrease the sensitivity to noise by increasing the slew rate of the bit clock or make the rise and fall times of serial bit clocks short, such that any noise around the transition produces a short duration noise-induced bit-clock pulse. This small high-frequency pulse will not have any impact on the SPORT or on the detection of the frame-sync. Sharpen edges as much as possible, if this is suitable and within EMI requirements.
  2. If possible, use internally generated bit-clocks and frame-syncs.
  3. Follow good PCB design practices. Shield RSCLK with respect to TSCLK lines to minimize coupling between the serial clocks.
  4. Separate RSCLK, TSCLK, and Frame Sync traces on the board to minimize coupling which occurs at the driving edge when FS switches.

A specific workaround for problems observed in Stereo Serial mode is to delay the frame-sync signal such that noise-induced bit-clock pulses do not start processing the frame-sync. This can be achieved if there is a larger serial resistor in the frame-sync trace than the one in the bit-clock trace. Frame-sync transitions should not cross the 50% point until the bit-clock crosses the 10% of VDD threshold (for a falling edge bit-clock) or the 90% threshold (for a rising edge bit-clock).

To improve immunity to noise, optional hysteresis can be enabled for input pins by setting bit 15 of the PLL_CTL register, followed by the appropriate PLL programming sequence.

05000269

Description

The internal voltage regulator is susceptible to supply and ground noise transients induced by high I/O activity, particularly in cases of high VDDext. This can result in a higher VDDint than the value that was programmed. In some cases, the value increases to a number outside the upper spec of the range in the data sheet. VDDint returns to the programmed value when the I/O activity diminishes or stops. Devices in BGA packages are more susceptible than devices in LQFP packages.

To date, increased voltages that have exceeded the upper end of the spec value have only been observed while running tests with artificially high I/O activity (e.g., when all bits of the address and data lines toggle every clock). Out-of-spec behavior has not been observed in any customer application running application code.

Workaround

This problem does not occur if an external voltage regulator is used.

To determine if the problem exists in your application, you should monitor the VDDint waveform under the following conditions/setup:

Not all parts are equally susceptible to this issue. Repeat the above monitoring on a minimum of 10 devices.

If the issue does occur, the value of VDDint will increase during periods of high I/O activity. If the max value of VDDint remains at or below the maximum VDDint, there will be no long term reliability issues, but power consumption will be higher.

Since the problem is a function of VDDext, I/O activity, and the programmed value of VDDint, the following techniques may mitigate/improve this issue:

05000270

Description

Heavy I/O activity can cause VDDint to decrease. The reference voltage, which is used to create the set point for the loop, is decreased by the supply noise. The voltage may drop to a level that is lower than the minimum required to meet your application's frequency of operations. The VDDint value returns to the programmed value once high I/O activity is halted.

Workaround

This issue does not occur when an external regulator is used.

To determine if the problem exists in your application, you should monitor the VDDint waveform under the following conditions/setup:

The following items can mitigate this issue:

05000275

Description

The PPI timing information and the corresponding diagrams in the ADSP-BF561: Blackfin® Processor Data Sheet (Rev. 0, 2/2005) was incorrect.

Workaround

Refer to the latest data sheet for the correct information.

05000418

Description

The ADSP-BF522/BF524/BF526 & ADSP-BF523/BF525/BF527(C) data sheet information for PPI timing specifications (tSFSPE (External Frame Sync Setup Before PPI_CLK) and tHFSPE (External Frame Sync Hold After PPI_CLK)) are not being met.

Workaround

Refer to the official ADI anomaly sheet for numbers to use.

05000421

Description

TWI Fall Time (Tof) may be less than the minimum I2C specification. This is not a functional issue, but may have an impact on signal integrity.

Workaround

None. Check your PCB's signal integrity.

05000422

Description

TWI input capacitance (Ci) may be may be more than the maximum I2C specification. This is not a functional issue, but may have an impact on signal integrity.

Workaround

None. Check your PCB's signal integrity.