Introduction For a complete set of general documentation please visit here: Memory Technology Devices Example Interfacing a NAND Flash to Blackfin's EBIU This interface is designed to work with NAND (Not AND (large flash memory type)) Flash devices that support the 'Chip Enable Don’t Care' feature connected directly to the Blackfin address/memory bus. If you are using a Blackfin supports an on chip NAND (Not AND (large flash memory type)) Flash Controller - you need the bf5xx_nand driver. Chip Enable Don’t Care In NAND (Not AND (large flash memory type)) devices with a standard Chip Enable signal, the data transfer of any read operation is aborted if Chip Enable goes High. For devices with the Chip Enable Don‘t Care feature, the Chip Enable can be used to select the NAND (Not AND (large flash memory type)) Flash, without affecting any current operation, as Chip Enable transitions during the data transfer of a read operation do not stop the operation. Chip Enable can be de-asserted during read, program or erase cycles, without interrupting the operation. This allows the microcontroller to share the I/O bus with other devices. Example Device: NAND128W3A2BN6E (ST Microelectronics) Blackfin , , NAND (Not AND (large flash memory type)) Flash A1 , → , Address Latch A2 , → , Command Latch AMSx , → , Chip Enable /ARE , → , NAND (Not AND (large flash memory type)) Read /AWE , → , NAND (Not AND (large flash memory type)) Write PFx , ← , NAND (Not AND (large flash memory type)) Busy PFx , → , NAND (Not AND (large flash memory type)) Write Protect D[0..7] , ↔ , NAND (Not AND (large flash memory type)) I/O[0..7] While it is possible, and may seem intuitive to connect the NAND (Not AND (large flash memory type)) Busy to the Blackfin's ARDY input, it is normally connected to a GPIO (General Purpose Input/Output) since we do not want a “Busy Wait”. Asserting ARDY will stall the processor, and not allow it to do other things while the flash is busy. Connecting it to a GPIO (General Purpose Input/Output) allows the Blackfin to do other things while the the NAND (Not AND (large flash memory type)) Busy is asserted. NAND (Not AND (large flash memory type))Busy is open-drain output that allows the Ready/Busy pins from several devices to be connected together. It therefore requires an external pull-up resistor. NAND Flash Driver See the mtd document for information on enabling support for NAND (Not AND (large flash memory type)) devices in general. The current driver is the generic platform NAND (Not AND (large flash memory type)) driver which can be found at linux-2.6.x/drivers/mtd/nand/plat_nand.c. Device Drivers ---> Memory Technology Device (MTD) support ---> NAND Device Support ---> <*> Support for generic platform NAND driver However, as the name implies, this is a generic driver, so most of the code there is not terribly interesting. The real meat of implementation is found in the specific boards file. Let's take a look at the example implementation for the BF537-STAMP. You can see that we treat this as a generic memory-mapped NAND (Not AND (large flash memory type)) device, and we overload just the control and ready functions to handle how we've glued it to the Blackfin. File system support (UBIFS) Please see the ubifs document for information on using UBIFS on a NAND (Not AND (large flash memory type)) device.