BF537 STAMP Board This is a low-cost development platform for the ADSP (Analog Digital Signal Processor)-BF537 Blackfin device. The STAMP board is part of the Blackfin/uClinux open source project. The schematics for the board as well as other related documents are available here. The ADSP (Analog Digital Signal Processor)-BF537 STAMP and the ADSP (Analog Digital Signal Processor)-BF537 EZkit are derived from the same design (they actually use the same base PCB -- the only difference is the silkscreen, and the bill of materials - there are less components on the STAMP to keep the price down, and make it more suitable for Linux Development). The STAMP board is commercially available and can be purchased from Digikey. The STAMP is designed to be used in conjunction with the GNU (GNU's Not Unix) Toolchain to test the capabilities of the ADSP (Analog Digital Signal Processor)-BF537 Blackfin processors. The GNU (GNU's Not Unix) Toolchain gives you the ability to perform advanced application code development and debug, such as: Create, compile, assemble, and link application programs written in C++, C and ADSP (Analog Digital Signal Processor)-BF537 assembly Load, run, step, halt, and set breakpoints in application program Read and write data and program memory Read and write core and peripheral registers Access to the ADSP (Analog Digital Signal Processor)-BF537 processor from a personal computer (PC) is achieved through either: Ethernet Serial JTAG (Joint Test Action Group - low level interface to cpu) An overview of some of the STAMP board's features are given below: ADSP (Analog Digital Signal Processor)-BF537 Blackfin device with JTAG (Joint Test Action Group - low level interface to cpu) interface 500MHz core clock 133MHz system clock (actual speed needs to be divisible by 25MHz, so max is 125MHz) 32M x 16bit external SDRAM (synchronous dynamic random access memory (system memory)) (64MBytes) 2M x 16bit external flash (4MBytes) 10/100 Mbps Ethernet Interface (via on chip MAC (Media Access Control (network interface)), connected via DMA (Direct Memory Access)) CAN (Controller Area Network - common automotive serial bus) TJA1041 transceiver with two modular connectors RS-232 UART (universal asynchronous receiver/transmitter) interface with DB9 (9 pin D-shell connector) serial connector JTAG (Joint Test Action Group - low level interface to cpu) ICE 14-pin header Six general-purpose LEDs, four general purpose push-buttons Discrete IDC Expansion ports for all processor peripherals Host tool requires either Windows XP(SP2), or Linux Host. STAMP boards containESD (electrostatic discharge)(electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. ProperESD (electrostatic discharge)precautions are recommended to avoid performance degradation or loss of functionality. Store unused Stamp boards in the protective shipping packages. Setting up the STAMP Hardware Please note - that the switch settings/setup information, assume that nothing is connected to the STAMP Board - if you have an add-on card (USB (Universal Serial Bus), TFT, etc), these directions may not work. To connect the STAMP board: Remove the STAMP board from the package. Be careful when handling the board to avoid the discharge of static electricity, which may damage some components. The figure below shows the default switches, Confirm that your board is set up in the default configuration before continuing.: Boot Mode Switch (SW16) switches should pointing to zero (0), for XIP, bypass boot-ROM. Connect FLASH to AMSn pins (SW6[1:4]) should all be away from the numbers, so flash is connected. Connect UART (universal asynchronous receiver/transmitter) (SW4[1:4]), should have pins 1 and 3 down towards the numbers, and pins 2 and 4 up. This will disable CTS/RTS support. Ensure UART (universal asynchronous receiver/transmitter) Jumper (JP9) is not populated, this will disconnect Loopback. Default UART (universal asynchronous receiver/transmitter) Settings in U-Boot should be 57600 baud, 8data bits, no parity, 1 stop bit (57600 8N1) Plug the provided power supply into J7 on the STAMP board. Visually verify that the green power LED (LED7) is on. Connect one end of the serial cable to an available serial port on your PC and the other end to UART0 on the STAMP board. Connect one end of a Ethernet cable to J4 of the STAMP board, and the other end to either a PC (requires cross over cable) or a Ethernet Hub (requires straight through cable). Hardware Initialization Initialization of the hardware is taken care of by both the Boot loader, and by the uClinux kernel. This initializes both the SDRAM (synchronous dynamic random access memory (system memory)), FLASH, and onboard peripherals like Ethernet and UART (universal asynchronous receiver/transmitter). If you are not using the provided Boot loader, or the uClinux kernel, you should review the appropriate data sheet, which can be downloaded from the STAMP project. Networking Networking capabilities are provided on the STAMP board via an the on chip IEEE 802.3 10/100 Ethernet MAC (Media Access Control (network interface)) and CAN (Controller Area Network - common automotive serial bus) 2.0B controller. The ADSP (Analog Digital Signal Processor)-BF537 STAMP includes an on-chip 10/100 Mbits/sec Ethernet MAC (Media Access Control (network interface)). The MAC (Media Access Control (network interface)) supports both 10-BaseT (10 Mbits/sec) and 100-BaseT (100 Mbits/sec) operations. The interface is exposed on the board, providing an easy connection between the STAMP and an existing TCP/IP network. uClinux includes a complete and robust open source TCP/IP software stack, running on the Blackfin architecture. This stack relies on the presence of the underlying uClinux operating system. Therefore, the STAMP and uClinux provide out of the box software and hardware connection for TCP/IP networking. U-Boot also includes a thin UDP protocol stack for such functions as DHCP (Dynamic Host Configuration Protocol), TFTP (Trivial File Transfer Protocol), BOOTP and RARP. The Controller Area Network interface uses an internal CAN (Controller Area Network - common automotive serial bus) 2.0B controller, and a Philips TJA1041 high-speed CAN (Controller Area Network - common automotive serial bus) transceiver. The PF14 programmable flag connects to the enable control input (EN). The PF15 programmable flag connects to the standby control input (~STB). The PF13 programmable flag connects to the error and power-on indication output (ERR). The PJ4 of the processor connects to the receive data output (RXD), and PJ5 connects to the transmit data input (TXD). The CAN (Controller Area Network - common automotive serial bus) interface can be disconnected from the processor by turning positions 1 though 4 of the SW2 switch to OFF. When in the OFF position, these signals can be used elsewhere on the board. The CAN (Controller Area Network - common automotive serial bus) interface contains two 4-position modular connectors. Using LEDs and Push Buttons UART Enable (SW4) Certain features of the UART0 may be controlled via the SW4 dip switch. UART (universal asynchronous receiver/transmitter) Feature , SW4 Switch Number CTS , 1 RX , 2 RTS , 3 Short RTS/CTS , 4 Dip switch 2 controls the Blackfin's ability to receive input from the UART (universal asynchronous receiver/transmitter). Note that the dip switches 1 and 3 are mutually exclusive with 4, so you can have either 1 and 3 on with 4 off, or 1 and 3 off with 4 on. So, to enable hardware flow control, you need to turn off 4 and turn on 1 and 3. Make sure you also disconnect JP9 (UART (universal asynchronous receiver/transmitter)Loop Jumper) RESET Button (SW9) The RESET push button resets all of the ICs on the board. Programmable Flag Push Buttons (SW5,SW10–13) Four push buttons, SW10–13, are provided for general-purpose user input. The buttons connect to the PF5–PF2 programmable flag pins of the processor. The push buttons are active HIGH and, when pressed, send a High (1) to the processor. The push button enable switch (SW5) is capable of disconnecting the push buttons from the PF. The programmable flag signals and their corresponding switches are shown below. Processor Programmable Flag Pin , Push Button Reference Designator , Push Button Name , SW5 Switch Number PF2 , SW13 , PB1 , 1 PF3 , SW12 , PB2 , 2 PF4 , SW11 , PB3 , 3 PF5 , SW10 , PB4 , 4 Boot mode (SW16) Position , Boot Mode , Misc Notes 0 , Execute from 16-bit external memory , Bypass Boot ROM and boot from parallel flash at 0×20000000, XIP the code (no LDR!) 1 , Boot from 16-bit memory , Execute an LDR stored in parallel flash at 0x20000000 2 , Reserved , Don't use it! 3 , Boot from SPI (Serial Peripheral Interface) memory , Boot from SPI (Serial Peripheral Interface) flash 4 , Boot from SPI (Serial Peripheral Interface) Host , slave mode, not tested 5 , Boot from Serial TWI (Two Wire Interface (I2C-compatible)) Memory , Boot from EEPROM/flash, not tested 6 , Boot from TWI (Two Wire Interface (I2C-compatible)) Host , slave mode, not tested 7 , Boot from UART (universal asynchronous receiver/transmitter) Host , recover via serial Power LED (LED7) When LED7 is lit (green), it indicates that power is being properly supplied to the board. Reset LEDs (LED8) When LED8 is lit, it indicates that the master reset of all the major ICs is active. User LEDs (LED1–6) Six LEDs connect to six general-purpose IO pins of the processor. The LEDs are active HIGH and are lit by writing a 1 to the correct PF signal. LED Reference Designator , Processor Programmable Flag Pin LED1 , PF6 LED2 , PF7 LED3 , PF8 LED4 , PF9 LED5 , PF10 LED6 , PF11 Connectors This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown. CAN Connectors (J5 and J11) Part Description , Manufacturer , Part Number , Mating Cable Modular Jack , AMP , 558872-1 , 4 conductor modular jack cable L-COM TSP3044 Ethernet Connector (J4) Part Description , Manufacturer , Part Number , Cable Ethernet Jack , Pulse , JK0-0025 , Patch or cross over cable RS-232 Connector (J6) Part Description , Manufacturer , Part Number , Cable DB9 (9 pin D-shell connector), Female, Vertical Mount , Digi-Key , 191-009-213-571-ND , Straight through Serial Cable Power Connector (J7) The power connector provides all of the power necessary to operate the STAMP board. Voltage input is 7.0 - 16V. Part Description , Manufacturer , Part Number , Cable 2.5 mm Power Jack , SWITCHCRAFT , RAPC712 , CUI Inc. DMS070214-P6P-SZ JTAG Connector (P4) The JTAG (Joint Test Action Group - low level interface to cpu) header is the connecting point for a JTAG (Joint Test Action Group - low level interface to cpu) in-circuit emulator pod. Pin 3 is missing to provide keying. Pin 3 in the mating connector should have a plug. IDC Connectors Peripheral , Connector , pins , Part Number , Mating connector SPORT0 , P6 , 34 , Digikey S2012-17-ND , Digikey S4217-ND SPORT1 , P7 , 34 , Digikey S2012-17-ND , Digikey S4217-ND PPI (Parallel Peripheral Interface) , P8 , 40 , Digikey S2012-20-ND , Digikey S4220-ND SPI (Serial Peripheral Interface) , P9 , 20 , Digikey S2012-10-ND , Digikey S4210-ND TWI (Two Wire Interface (I2C-compatible)) , P10 , 20 , Digikey S2012-10-ND , Digikey S4210-ND TIMERS , P11 , 20 , Digikey S2012-05-ND , Digikey S4205-ND UART1 , P12 , 10 , Digikey S2012-05-ND , Digikey S4205-ND External Bus Interface Unit The external bus interface unit (EBIU (External Bus Interface Unit)) connects external memory to the ADSP (Analog Digital Signal Processor)-BF537 processor. The unit includes a 16-bit wide data bus, an address bus, and a control bus. On the STAMP, the EBIU (External Bus Interface Unit) connects to the SDRAM (synchronous dynamic random access memory (system memory)), flash, and expansion interfaces. 64 Mbytes (32M x 16 bits) of SDRAM (synchronous dynamic random access memory (system memory)) connect to the synchronous memory select 0 pin (~SMS0). Note that SDRAM (synchronous dynamic random access memory (system memory)) clock is the processor’s clock out (CLK OUT), which must not exceed 133 MHz (Megahertz). The flash memory device connects to the asynchronous memory select signals, ~AMS3 through ~AMS0. The device provides a total of 4 Mbytes of flash memory. The processor can use this memory for both booting and storing information during normal operation. Setting the MAC Address To understand how to set the MAC (Media Access Control (network interface)) address, you need to understand where U-Boot looks for a MAC (Media Access Control (network interface)) address, and then how it passes that MAC (Media Access Control (network interface)) address to the kernel. When the system boots up on the STAMP Board, U-Boot looks: In the environmental variable ethaddr In the parallel Flash at location 0x20300000 (the first bytes of the last sector). If U-Boot can find a valid MAC (Media Access Control (network interface)) address (which is anything except FF:FF:FF:FF:FF:FF), it programs this into the Ethernet MAC (Media Access Control (network interface)) of the BF537. When the Blackfin Ethernet kernel driver is loaded it also looks for a valid MAC (Media Access Control (network interface)). Once it finds one, it also programs the MAC (Media Access Control (network interface)) and stops looking. In the MAC (Media Access Control (network interface)) (if U-Boot programmed it) In the parallel Flash at location 0x20300000 (the first bytes of the last sector). Programs a random/private MAC (Media Access Control (network interface)) address, as allowed by the IEEE - these MAC (Media Access Control (network interface)) addresses are normally thrown away by most routers, as not to polute the internet. Therefore, in a properly configured platform (one in which U-Boot loads the MAC (Media Access Control (network interface)) address, into the MAC (Media Access Control (network interface))), there is no need to worry about the MAC (Media Access Control (network interface)) address in the kernel. The MAC (Media Access Control (network interface)) address of the BF537-STAMP (and BF537-EZKIT) are stored in the main flash. Doing theprotect off all; erase allbelow, is not meant as instructions, it is an example of whatNOTto do This means if you do something like: bf537> protect off all bf537> erase all You will end up with a MAC (Media Access Control (network interface)) address of FF:FF:FF:FF:FF:FF. To set the MAC (Media Access Control (network interface)) address, the best way is to, set the MAC (Media Access Control (network interface)) address is RAM (by using the memory modify command), and then copy this into flash. This can be done in the following way. In the below example, the MAC (Media Access Control (network interface)) address will be set to 00:E0:22:FE:07:91 bf537> mm.b Usage: mm - memory modify (auto-incrementing) bf537> mm.b 0x0 00000000: 00 ? 00 00000001: 00 ? e0 00000002: 00 ? 22 00000003: 00 ? fe 00000004: 00 ? 07 00000005: 00 ? 91 00000006: 00 ? bf537> bf537> md.b 0x0 0x06 00000000: 00 e0 22 fe 07 91 bf537> protect off 0x203F0000 0x203FFFFF bf537> erase 0x203F0000 0x203FFFFF bf537> cp.b 0x0 0x203F0000 0x06 To interrupt the auto-incrementing of the memory modify, press CONTROL-C twice Clearing the MAC Address Keep in mind that the MAC (Media Access Control (network interface)) address is cached in the environment in the ethaddr variable. If you want to change your MAC (Media Access Control (network interface)) address, you'll have to update both the flash and the environment.