We are doing 178 byte writes to an SPI device. About 20% of the time there are only 175 bytes written to the SPI bus. 

The problem is in drivers/char/spi_bfin5xx.c

The HRM says there must be two SUCCESSIVE reads in a row of the SPI_STAT register, in which the TXS bit is clear.

In the dma_irq_handler the following changes need to be made...

The current implementation does:
     while( bfin_read_SPI_STAT() & TXS )
        ;
     while( bfin_read_SPI_STAT() & TXS )
        ;

This only guarantees that on two occasions the TXS bit was clear. It does not guarantee that they are successive!

A fix is:
    
    if (drv_data->tx != NULL) {
        int done = 0;
        while (!done) {
            while (bfin_read_SPI_STAT() & TXS)
                ; // got the first one
            if (bfin_read_SPI_STAT() & TXS)
                continue;
            else {
                done = 1;
                break;
            }
        }
    }

This fixes the dropped bytes at end of DMA SPI transfers!