Blackfin One v2.0.0 Bugs

Your boards may or may not have the following issues depending on the files you used to build the PCB. Please verify and make any corrections.

Silkscreen

The silk screen names of R73 and C106 are swapped.

The correct layout is

• C106 connects GND (pin 15) and VDD (pin 23) on U18
• R73 connects INT (pin 34) on U18 to PF15 (pin 27 on U1)

Pull-Downs

Note from sch 1. Proposed address decoding, PF13=0 selects flash, PF13=1 selects Ethernet chips.

PF13 should be pulled down to GND through a 10k resistor. A good place to add this resistor is to the right of the CPLD (U22). See resistor_pf13.jpg

Pull-Ups

FLARDY is a signal from the CPLD which controls the RDY/BUSY signal on the parallel flash chip U3. This is an active low signal which means that it should be pulled up to Vcc to ensure that the RDY signal doesn't go low unless it is actively driven low by the CPLD.

FLARDY should be pulled up to +3.3V with 10KOhm resistor. See the resistor_flardy.jpg for placement.

Shorts

The BFJTAG2 header has 2 shorts that tie signals to GND. The thermal pads on pin 7 and 13 short with the traces that come from BFJTAG2 pin 6 and pin 10 of U22 respectively.

• Cut the thermal that shorts pin 7 and pin 6 on header BFJTAG2
• Cut the thermal that shorts pin 13 on BFJTAG2 to pin 10 of U22